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- library IEEE;
- use IEEE.std_logic_1164.all;
- use IEEE.std_logic_arith.all;
- use IEEE.std_logic_unsigned.all;
- entity realdig is
- Port (
- reloj, pausa, reset1: in std_logic;
- L1, L2, L3, L4: out std_logic_vector (6 downto 0));
- end realdig;
- architecture behavioral of realdig is
- signal segundo: std_logic;
- signal rapido: std_logic;
- signal n: std_logic;
- signal Qum: std_logic_vector(3 downto 0);
- signal Qdm: std_logic_vector(3 downto 0);
- signal e: std_logic;
- signal Quh: std_logic_vector(3 downto 0);
- signal Qdh: std_logic_vector(3 downto 0);
- signal z: std_logic;
- signal u: std_logic;
- signal d: std_logic;
- signal reset: std_logic;
- begin
- divisor: process (reloj)
- variable cuenta: std_logic_vector(27 downto 0) := X"0000000";
- begin
- if rising_edge (reloj) then
- if cuenta=X"48009E0" then
- cuenta:= X"0000000";
- else
- cuenta:= cuenta +1;
- end if;
- end if;
- segundo <= cuenta(22);
- rapido <= cuenta(10);
- end process;
- unidades: process (segundo)
- variable cuenta: std_logic_vector(3 downto 0) := "0000";
- begin
- if rising_edge (segundo) then
- if pausa = '1' then
- else
- if cuenta ="1001" then
- cuenta:="0000";
- n <= '1';
- else
- cuenta:= cuenta +1;
- n <= '0';
- end if;
- end if;
- if reset1 = '0' then
- cuenta:="0000";
- n<='1';
- end if;
- end if;
- Qum <= cuenta;
- end process;
- decenas: process (n)
- variable cuenta: std_logic_vector(3 downto 0) := "0000";
- begin
- if rising_edge (n) then
- if pausa = '1' then
- else
- if cuenta ="0101" then
- cuenta:="0000";
- e <= '1';
- else
- cuenta:= cuenta +1;
- e<= '0';
- end if;
- end if;
- if reset1 = '0' then
- cuenta:="0000";
- e<='1';
- end if;
- end if;
- Qdm <= cuenta;
- end process;
- HoraU: Process(e,reset)
- variable cuenta: std_logic_vector(3 downto 0):="0000";
- begin
- if rising_edge(e) then
- if pausa = '1' then
- else
- if cuenta="1001" then
- cuenta:= "0000";
- z<='1';
- else
- cuenta:=cuenta+1;
- z<='0';
- end if;
- end if;
- if reset='1' then
- cuenta:="0000";
- end if;
- if reset1 = '0' then
- cuenta:="0000";
- z<='1';
- end if;
- end if;
- Quh<=cuenta;
- u<=cuenta(2);
- end Process;
- HoraD: Process(z, reset)
- variable cuenta: std_logic_vector(3 downto 0):="0000";
- begin
- if rising_edge(z) then
- if pausa = '1' then
- else
- if cuenta="0010" then
- cuenta:= "0000";
- else
- cuenta:=cuenta+1;
- end if;
- end if;
- if reset='1' then
- cuenta:="0000";
- end if;
- if reset1 = '0' then
- cuenta:="0000";
- end if;
- end if;
- Qdh<=cuenta;
- d <=cuenta(1);
- end Process;
- inicia: process (u,d)
- begin
- reset <= (u and d);
- end process;
- with Qum select
- L1 <= "1000000" when "0000", --0
- "1111001" when "0001", --1
- "0100100" when "0010", --2
- "0110000" when "0011", --3
- "0011001" when "0100", --4
- "0010010" when "0101", --5
- "0000010" when "0110", --6
- "1111000" when "0111", --7
- "0000000" when "1000", --8
- "0010000" when "1001", --9
- "1000000" when others; --F
- with Qdm select
- L2 <= "1000000" when "0000", --0
- "1111001" when "0001", --1
- "0100100" when "0010", --2
- "0110000" when "0011", --3
- "0011001" when "0100", --4
- "0010010" when "0101", --5
- "0000010" when "0110", --6
- "1111000" when "0111", --7
- "0000000" when "1000", --8
- "0010000" when "1001", --9
- "1000000" when others; --F
- with Quh select
- L3 <= "1000000" when "0000", --0
- "1111001" when "0001", --1
- "0100100" when "0010", --2
- "0110000" when "0011", --3
- "0011001" when "0100", --4
- "0010010" when "0101", --5
- "0000010" when "0110", --6
- "1111000" when "0111", --7
- "0000000" when "1000", --8
- "0010000" when "1001", --9
- "1000000" when others; --F
- with Qdh select
- L4 <= "1000000" when "0000", --0
- "1111001" when "0001", --1
- "0100100" when "0010", --2
- "0110000" when "0011", --3
- "0011001" when "0100", --4
- "0010010" when "0101", --5
- "0000010" when "0110", --6
- "1111000" when "0111", --7
- "0000000" when "1000", --8
- "0010000" when "1001", --9
- "1000000" when others; --F
- end Behavioral;
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