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- tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
- ==========================================================================
- == Memory bandwidth tests ==
- == ==
- == Note 1: 1MB = 1000000 bytes ==
- == Note 2: Results for 'copy' tests show how many bytes can be ==
- == copied per second (adding together read and writen ==
- == bytes would have provided twice higher numbers) ==
- == Note 3: 2-pass copy means that we are using a small temporary buffer ==
- == to first fetch data into it, and only then write it to the ==
- == destination (source -> L1 cache, L1 cache -> destination) ==
- == Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
- == brackets ==
- ==========================================================================
- C copy backwards : 6799.8 MB/s (1.3%)
- C copy backwards (32 byte blocks) : 6787.4 MB/s (1.1%)
- C copy backwards (64 byte blocks) : 6817.8 MB/s (0.5%)
- C copy : 6777.8 MB/s (0.4%)
- C copy prefetched (32 bytes step) : 6755.4 MB/s (0.6%)
- C copy prefetched (64 bytes step) : 6755.4 MB/s (0.5%)
- C 2-pass copy : 6346.9 MB/s (0.4%)
- C 2-pass copy prefetched (32 bytes step) : 6542.7 MB/s (0.3%)
- C 2-pass copy prefetched (64 bytes step) : 6546.1 MB/s (0.7%)
- C fill : 10658.5 MB/s (0.6%)
- C fill (shuffle within 16 byte blocks) : 10642.1 MB/s (0.6%)
- C fill (shuffle within 32 byte blocks) : 10603.8 MB/s (0.3%)
- C fill (shuffle within 64 byte blocks) : 10644.7 MB/s (0.3%)
- ---
- standard memcpy : 10487.3 MB/s (0.5%)
- standard memset : 26842.2 MB/s (0.9%)
- ---
- MOVSB copy : 9393.9 MB/s (0.2%)
- MOVSD copy : 9155.0 MB/s (1.6%)
- SSE2 copy : 6780.5 MB/s (0.4%)
- SSE2 nontemporal copy : 10688.2 MB/s (0.3%)
- SSE2 copy prefetched (32 bytes step) : 6751.9 MB/s (0.4%)
- SSE2 copy prefetched (64 bytes step) : 6744.2 MB/s (0.5%)
- SSE2 nontemporal copy prefetched (32 bytes step) : 10707.7 MB/s (1.3%)
- SSE2 nontemporal copy prefetched (64 bytes step) : 10698.8 MB/s (1.3%)
- SSE2 2-pass copy : 6457.4 MB/s (0.5%)
- SSE2 2-pass copy prefetched (32 bytes step) : 6373.7 MB/s (0.4%)
- SSE2 2-pass copy prefetched (64 bytes step) : 6358.8 MB/s (0.5%)
- SSE2 2-pass nontemporal copy : 4915.7 MB/s (0.3%)
- SSE2 fill : 10525.7 MB/s (0.5%)
- SSE2 nontemporal fill : 19563.3 MB/s
- ==========================================================================
- == Framebuffer read tests. ==
- == ==
- == Many ARM devices use a part of the system memory as the framebuffer, ==
- == typically mapped as uncached but with write-combining enabled. ==
- == Writes to such framebuffers are quite fast, but reads are much ==
- == slower and very sensitive to the alignment and the selection of ==
- == CPU instructions which are used for accessing memory. ==
- == ==
- == Many x86 systems allocate the framebuffer in the GPU memory, ==
- == accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
- == PCI-E is asymmetric and handles reads a lot worse than writes. ==
- == ==
- == If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
- == or preferably >300 MB/s), then using the shadow framebuffer layer ==
- == is not necessary in Xorg DDX drivers, resulting in a nice overall ==
- == performance improvement. For example, the xf86-video-fbturbo DDX ==
- == uses this trick. ==
- ==========================================================================
- MOVSD copy (from framebuffer) : 206.2 MB/s (1.6%)
- MOVSD 2-pass copy (from framebuffer) : 225.8 MB/s
- SSE2 copy (from framebuffer) : 140.1 MB/s (0.1%)
- SSE2 2-pass copy (from framebuffer) : 139.5 MB/s
- ==========================================================================
- == Memory latency test ==
- == ==
- == Average time is measured for random memory accesses in the buffers ==
- == of different sizes. The larger is the buffer, the more significant ==
- == are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
- == accesses. For extremely large buffer sizes we are expecting to see ==
- == page table walk with several requests to SDRAM for almost every ==
- == memory access (though 64MiB is not nearly large enough to experience ==
- == this effect to its fullest). ==
- == ==
- == Note 1: All the numbers are representing extra time, which needs to ==
- == be added to L1 cache latency. The cycle timings for L1 cache ==
- == latency can be usually found in the processor documentation. ==
- == Note 2: Dual random read means that we are simultaneously performing ==
- == two independent memory accesses at a time. In the case if ==
- == the memory subsystem can't handle multiple outstanding ==
- == requests, dual random read has the same timings as two ==
- == single reads performed one after another. ==
- ==========================================================================
- block size : single random read / dual random read, [MADV_NOHUGEPAGE]
- 1024 : 0.0 ns / 0.0 ns
- 2048 : 0.0 ns / 0.0 ns
- 4096 : 0.0 ns / 0.0 ns
- 8192 : 0.0 ns / 0.0 ns
- 16384 : 0.0 ns / 0.0 ns
- 32768 : 0.0 ns / 0.1 ns
- 65536 : 1.1 ns / 1.5 ns
- 131072 : 1.6 ns / 1.9 ns
- 262144 : 2.3 ns / 3.0 ns
- 524288 : 6.7 ns / 8.6 ns
- 1048576 : 9.1 ns / 10.6 ns
- 2097152 : 10.4 ns / 11.3 ns
- 4194304 : 12.0 ns / 12.9 ns
- 8388608 : 30.7 ns / 45.7 ns
- 16777216 : 53.5 ns / 72.7 ns
- 33554432 : 67.0 ns / 83.2 ns
- 67108864 : 72.8 ns / 89.5 ns
- block size : single random read / dual random read, [MADV_HUGEPAGE]
- 1024 : 0.0 ns / 0.0 ns
- 2048 : 0.0 ns / 0.0 ns
- 4096 : 0.0 ns / 0.0 ns
- 8192 : 0.0 ns / 0.0 ns
- 16384 : 0.0 ns / 0.0 ns
- 32768 : 0.0 ns / 0.0 ns
- 65536 : 1.1 ns / 1.5 ns
- 131072 : 1.6 ns / 2.0 ns
- 262144 : 1.9 ns / 2.1 ns
- 524288 : 5.5 ns / 7.3 ns
- 1048576 : 7.3 ns / 8.7 ns
- 2097152 : 8.3 ns / 9.1 ns
- 4194304 : 8.7 ns / 9.2 ns
- 8388608 : 25.2 ns / 37.2 ns
- 16777216 : 47.7 ns / 63.7 ns
- 33554432 : 58.6 ns / 71.8 ns
- 67108864 : 63.8 ns / 74.7 ns
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