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By: a guest on Jul 16th, 2012  |  syntax: None  |  size: 0.69 KB  |  views: 29  |  expires: Never
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  1. /* processor status */
  2. enum {
  3.     PSW_IE    = (1<<0),
  4.     PSW_EIE   = (1<<1),
  5.     PSW_BIE   = (1<<2),
  6.     PSW_ITLB  = (1<<4),
  7.     PSW_EITLB = (1<<5),
  8.     PSW_BITLB = (1<<6),
  9.     PSW_DTLB  = (1<<7),
  10.     PSW_EDTLB = (1<<8),
  11.     PSW_BDTLB = (1<<9),
  12.     PSW_USR   = (1<<10),
  13.     PSW_EUSR  = (1<<11),
  14.     PSW_BUSR  = (1<<12),
  15. };
  16.  
  17.  
  18. /* TLBCTRL commands */
  19. enum {
  20.     ITLB_FLUSH        = 0x02,
  21.     DTLB_FLUSH        = 0x03,
  22.     ITLB_UPDATE       = 0x04,
  23.     DTLB_UPDATE       = 0x05,
  24.     ITLB_INVALIDATE   = 0x20,
  25.     DTLB_INVALIDATE   = 0x21,
  26. };
  27.  
  28. /* CSRs */
  29. enum {
  30. ...
  31.     CSR_PSW       = 0x1c,
  32.     CSR_TLBCTRL   = 0x1d,
  33.     CSR_TLBVADDR  = 0x1e,
  34.     CSR_TLBPADDR  = 0x1f,
  35. };
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