`define STATUS_REGISTER 5'd12
`define CAUSE_REGISTER  5'd13
`define EPC_REGISTER    5'd14

module cp0(rd_data, EPC, TakenInterrupt,
           regnum, wr_data, next_pc, TimerInterrupt,
           MTC0, ERET, clock, reset);
    output [31:0] rd_data, status_register, cause_register;
    output [29:0] EPC;
    output        TakenInterrupt;
    input   [4:0] regnum;
    input  [31:0] wr_data;
    input  [29:0] next_pc;
    input         TimerInterrupt, MTC0, ERET, clock, reset;

    // your Verilog for coprocessor 0 goes here

    // Status Register
    assign status_register[31:16] = 0;
    assign status_register[15:8] = user_status[15:8];
    assign status_register[7:2] = 0;
    assign status_register[1] = exception_level;
    assign status_register[0] = user_status[0];

    // Cause Register
    assign cause_register[31:16] = 0;
    assign cause_register[15] = TimerInterrupt;
    assign cause_register[14:0] = 0;

    // Decoder
    decoder32 d32(decoder_out, regnum, MTC0);

    // Exception Level
    dffe exception_level_dffe(exception_level, 1'b1, clock, TakenInterrupt, exception_level_reset);
    wire exception_level_reset = ERET | TakenInterrupt;

    // EPC Register
    register #(30,) EPC_register(EPC, write_next_out, clock, EPC_enable, reset);
    wire EPC_enable = decoder_out[14] | TakenInterrupt;

    // User Register
    register #(32,) user_status(user_status, wr_data, clock, decoder_out[12], reset);

    // Muxes
    mux2v #(30) write_next(write_next_out, wr_data[31:2], next_pc, TakenInterrupt);
    wire [31:0] 32EPC = {EPC, 2'b0};
    mux32v #(32) m32(rd_data, 0,0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, status_register, cause_register, 32EPC, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, regnum);

    // TakenInterrupt
    wire TakenInterrupt = (cause_register[15] & status_register[15]) & (~(status_register[1]) & status_register[0]);

endmodule