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  3. coreboot- Mon Dec 10 16:18:26 PST 2012 starting...
  4. Setting up static southbridge registers... done.
  5. Disabling Watchdog reboot... done.
  6. Setting up static northbridge registers... done.
  7. Boot Count incremented to 3347
  8. Initializing Graphics...
  9. Back from sandybridge_early_initialization()
  10. Google Chrome set keyboard backlight: f2 status (0)
  11. SMBus controller enabled.
  12. spd index 0
  13. CBFS: Looking for 'spd.bin'
  14. CBFS: found.
  15. CPU id(306a9): Intel(R) Core(TM) i5-3427U CPU @ 1.80GHz
  16. AES supported, TXT supported, VT supported
  17. PCH type: HM75, device id: 1e5d, rev id 4
  18. Intel ME early init
  19. Intel ME firmware is ready
  20. ME: Requested 16MB UMA
  21. Starting UEFI PEI System Agent
  22. Read scrambler seed 0x00005cd9 from CMOS 0x98
  23. Read S3 scrambler seed 0x00007e54 from CMOS 0x9c
  24. FMAP: Found "FMAP" version 1.0 at ffe10000.
  25. FMAP: base = 0 size = 800000 #areas = 30
  26. FMAP: area RW_MRC_CACHE found
  27. FMAP: offset: 3e0000
  28. FMAP: size: 65536 bytes
  29. FMAP: No valid base address, using 0xff800000
  30. FMAP: RW_MRC_CACHE at ffbe0000 (offset 3e0000)
  31. find_current_mrc_cache_local: picked entry 1 from cache block
  32. prepare_mrc_cache: at ffbe1010, size bb0 checksum d14e
  33. CBFS: Looking for 'mrc.bin'
  34. CBFS: found.
  35. System Agent: Starting up...
  36. System Agent: Initializing PCH
  37. System Agent: Initializing PCH (SMBUS)
  38. System Agent: Initializing PCH (USB)
  39. System Agent: Initializing PCH (SA Init)
  40. SA PciExpress skipped (pcie_init is 0)
  41. System Agent: Initializing PCH (Me UMA)
  42. System Agent: Initializing Memory
  43. System Agent: Done.
  44. System Agent Version 1.6.0 Build 0
  45. ME: FW Partition Table : OK
  46. ME: Bringup Loader Failure : NO
  47. ME: Firmware Init Complete : NO
  48. ME: Manufacturing Mode : NO
  49. ME: Boot Options Present : NO
  50. ME: Update In Progress : NO
  51. ME: Current Working State : Normal
  52. ME: Current Operation State : Bring up
  53. ME: Current Operation Mode : Normal
  54. ME: Error Code : No Error
  55. ME: Progress Phase : BUP Phase
  56. ME: Power Management Event : Pseudo-global reset
  57. ME: Progress Phase State : 0x50
  58. memcfg DDR3 clock 1600 MHz
  59. memcfg channel assignment: A: 0, B 1, C 2
  60. memcfg channel[0] config (00680008):
  61. ECC inactive
  62. enhanced interleave mode on
  63. rank interleave on
  64. DIMMA 2048 MB width x16 single rank, selected
  65. DIMMB 0 MB width x8 single rank
  66. memcfg channel[1] config (00680008):
  67. ECC inactive
  68. enhanced interleave mode on
  69. rank interleave on
  70. DIMMA 2048 MB width x16 single rank, selected
  71. DIMMB 0 MB width x8 single rank
  72. Re-Initializing CBMEM area to 0xacec0000
  73. Initializing CBMEM area to 0xacec0000 (1310720 bytes)
  74. Adding CBMEM entry as no. 1
  75. Relocate MRC DATA from ff7e3237 to acec0200 (2992 bytes)
  76. Save scrambler seed 0x0000a61f to CMOS 0x98
  77. Save s3 scrambler seed 0x00005cd9 to CMOS 0x9c
  78. Re-Initializing CBMEM area to 0xacec0000
  79. Adding CBMEM entry as no. 2
  80. Adding CBMEM entry as no. 3
  81. Loading image.
  82. CBFS: Looking for 'fallback/coreboot_ram'
  83. CBFS: found.
  84. CBFS: loading stage fallback/coreboot_ram @ 0x100000 (368640 bytes), entry @ 0x100000
  85. Jumping to image.
  86. coreboot- Mon Dec 10 16:18:26 PST 2012 booting...
  87. Enumerating buses...
  88. Show all devs...Before device enumeration.
  89. Root Device: enabled 1
  90. APIC_CLUSTER: 0: enabled 1
  91. APIC: 00: enabled 1
  92. APIC: acac: enabled 0
  93. PCI_DOMAIN: 0000: enabled 1
  94. PCI: 00:00.0: enabled 1
  95. PCI: 00:02.0: enabled 1
  96. PCI: 00:16.0: enabled 1
  97. PCI: 00:16.1: enabled 0
  98. PCI: 00:16.2: enabled 0
  99. PCI: 00:16.3: enabled 0
  100. PCI: 00:19.0: enabled 0
  101. PCI: 00:1a.0: enabled 1
  102. PCI: 00:1b.0: enabled 1
  103. PCI: 00:1c.0: enabled 0
  104. PCI: 00:1c.1: enabled 0
  105. PCI: 00:1c.2: enabled 1
  106. PCI: 00:1c.3: enabled 0
  107. PCI: 00:1c.4: enabled 0
  108. PCI: 00:1c.5: enabled 0
  109. PCI: 00:1c.6: enabled 0
  110. PCI: 00:1c.7: enabled 0
  111. PCI: 00:1d.0: enabled 1
  112. PCI: 00:1e.0: enabled 0
  113. PCI: 00:1f.0: enabled 1
  114. PNP: 00ff.1: enabled 1
  115. PCI: 00:1f.2: enabled 1
  116. PCI: 00:1f.3: enabled 1
  117. PCI: 00:1f.5: enabled 0
  118. PCI: 00:1f.6: enabled 1
  119. Compare with tree...
  120. Root Device: enabled 1
  121. APIC_CLUSTER: 0: enabled 1
  122. APIC: 00: enabled 1
  123. APIC: acac: enabled 0
  124. PCI_DOMAIN: 0000: enabled 1
  125. PCI: 00:00.0: enabled 1
  126. PCI: 00:02.0: enabled 1
  127. PCI: 00:16.0: enabled 1
  128. PCI: 00:16.1: enabled 0
  129. PCI: 00:16.2: enabled 0
  130. PCI: 00:16.3: enabled 0
  131. PCI: 00:19.0: enabled 0
  132. PCI: 00:1a.0: enabled 1
  133. PCI: 00:1b.0: enabled 1
  134. PCI: 00:1c.0: enabled 0
  135. PCI: 00:1c.1: enabled 0
  136. PCI: 00:1c.2: enabled 1
  137. PCI: 00:1c.3: enabled 0
  138. PCI: 00:1c.4: enabled 0
  139. PCI: 00:1c.5: enabled 0
  140. PCI: 00:1c.6: enabled 0
  141. PCI: 00:1c.7: enabled 0
  142. PCI: 00:1d.0: enabled 1
  143. PCI: 00:1e.0: enabled 0
  144. PCI: 00:1f.0: enabled 1
  145. PNP: 00ff.1: enabled 1
  146. PCI: 00:1f.2: enabled 1
  147. PCI: 00:1f.3: enabled 1
  148. PCI: 00:1f.5: enabled 0
  149. PCI: 00:1f.6: enabled 1
  150. scan_static_bus for Root Device
  151. APIC_CLUSTER: 0 enabled
  152. PCI_DOMAIN: 0000 enabled
  153. PCI_DOMAIN: 0000 scanning...
  154. PCI: pci_scan_bus for bus 00
  155. PCI: 00:00.0 [8086/0154] ops
  156. Normal boot.
  157. PCI: 00:00.0 [8086/0154] enabled
  158. PCI: 00:02.0 [8086/0000] ops
  159. PCI: 00:02.0 [8086/0166] enabled
  160. PCI: 00:16.0 [8086/1e3a] bus ops
  161. PCI: 00:16.0 [8086/1e3a] enabled
  162. PCI: 00:16.1: Disabling device
  163. PCI: 00:16.2: Disabling device
  164. PCI: 00:16.3: Disabling device
  165. PCI: 00:19.0: Disabling device
  166. PCI: 00:1a.0 [8086/0000] ops
  167. PCI: 00:1a.0 [8086/1e2d] enabled
  168. PCI: 00:1b.0 [8086/0000] ops
  169. PCI: 00:1b.0 [8086/1e20] enabled
  170. PCH: PCIe Root Port coalescing is enabled
  171. PCI: 00:1c.0: Disabling device
  172. PCI: 00:1c.0: check set enabled
  173. PCI: 00:1c.1: Disabling device
  174. PCH: Remap PCIe function 2 to 0
  175. PCI: 00:1c.2 [8086/0000] bus ops
  176. PCI: 00:1c.2 [8086/1e14] enabled
  177. PCI: 00:1c.3: Disabling device
  178. PCI: 00:1c.4: Disabling device
  179. PCI: 00:1c.4: check set enabled
  180. PCI: 00:1c.5: Disabling device
  181. PCI: 00:1c.6: Disabling device
  182. PCI: 00:1c.7: Disabling device
  183. PCH: RPFN 0x76543210 -> 0xfedcb09a
  184. PCH: PCIe map 1c.0 -> 1c.2
  185. PCH: PCIe map 1c.2 -> 1c.0
  186. PCI: 00:1d.0 [8086/0000] ops
  187. PCI: 00:1d.0 [8086/1e26] enabled
  188. PCI: 00:1e.0: Disabling device
  189. PCI: 00:1f.0 [8086/0000] bus ops
  190. PCI: 00:1f.0 [8086/1e5d] enabled
  191. PCI: 00:1f.2 [8086/0000] ops
  192. PCI: 00:1f.2 [8086/1e01] enabled
  193. PCI: 00:1f.3 [8086/0000] bus ops
  194. PCI: 00:1f.3 [8086/1e22] enabled
  195. PCI: 00:1f.5: Disabling device
  196. PCI: 00:1f.6 [8086/1e24] enabled
  197. scan_static_bus for PCI: 00:16.0
  198. scan_static_bus for PCI: 00:16.0 done
  199. do_pci_scan_bridge for PCI: 00:1c.0
  200. PCI: pci_scan_bus for bus 01
  201. PCI: 01:00.0 [168c/0034] enabled
  202. PCI: pci_scan_bus returning with max=001
  203. Capability: type 0x01 @ 0x40
  204. Capability: type 0x05 @ 0x50
  205. Capability: type 0x10 @ 0x70
  206. Capability: type 0x10 @ 0x40
  207. Enabling Common Clock Configuration
  208. ASPM: Enabled L0s and L1
  209. do_pci_scan_bridge returns max 1
  210. scan_static_bus for PCI: 00:1f.0
  211. PNP: 00ff.1 enabled
  212. PNP: 00ff.0 enabled
  213. scan_static_bus for PCI: 00:1f.0 done
  214. scan_static_bus for PCI: 00:1f.3
  215. scan_static_bus for PCI: 00:1f.3 done
  216. PCI: pci_scan_bus returning with max=001
  217. scan_static_bus for Root Device done
  218. done
  219. Setting up VGA for PCI: 00:02.0
  220. Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
  221. Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
  222. Allocating resources...
  223. Reading resources...
  224. Root Device read_resources bus 0 link: 0
  225. APIC_CLUSTER: 0 read_resources bus 0 link: 0
  226. APIC: 00 missing read_resources
  227. APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
  228. PCI_DOMAIN: 0000 read_resources bus 0 link: 0
  229. Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
  230. PCI: 00:1c.0 read_resources bus 1 link: 0
  231. PCI: 00:1c.0 read_resources bus 1 link: 0 done
  232. PCI: 00:1f.0 read_resources bus 0 link: 0
  233. PNP: 00ff.1 missing read_resources
  234. PCI: 00:1f.0 read_resources bus 0 link: 0 done
  235. PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
  236. Root Device read_resources bus 0 link: 0 done
  237. Done reading resources.
  238. Show resources in subtree (Root Device)...After reading.
  239. Root Device child on link 0 APIC_CLUSTER: 0
  240. APIC_CLUSTER: 0 child on link 0 APIC: 00
  241. APIC: 00
  242. APIC: acac
  243. PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  244. PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  245. PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
  246. PCI: 00:00.0
  247. PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
  248. PCI: 00:02.0
  249. PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
  250. PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
  251. PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
  252. PCI: 00:16.0
  253. PCI: 00:16.0 resource base 0 size 10 align 4 gran 4 limit ffffffffffffffff flags 201 index 10
  254. PCI: 00:16.1
  255. PCI: 00:16.2
  256. PCI: 00:16.3
  257. PCI: 00:19.0
  258. PCI: 00:1a.0
  259. PCI: 00:1a.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
  260. PCI: 00:1b.0
  261. PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
  262. PCI: 00:1c.2
  263. PCI: 00:1c.1
  264. PCI: 00:1c.0 child on link 0 PCI: 01:00.0
  265. PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
  266. PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
  267. PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
  268. PCI: 01:00.0
  269. PCI: 01:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 201 index 10
  270. PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
  271. PCI: 00:1c.3
  272. PCI: 00:1c.4
  273. PCI: 00:1c.5
  274. PCI: 00:1c.6
  275. PCI: 00:1c.7
  276. PCI: 00:1d.0
  277. PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
  278. PCI: 00:1e.0
  279. PCI: 00:1f.0 child on link 0 PNP: 00ff.1
  280. PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
  281. PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
  282. PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
  283. PNP: 00ff.1
  284. PNP: 00ff.0
  285. PCI: 00:1f.2
  286. PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
  287. PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
  288. PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
  289. PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
  290. PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
  291. PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
  292. PCI: 00:1f.3
  293. PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
  294. PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
  295. PCI: 00:1f.5
  296. PCI: 00:1f.6
  297. PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
  298. PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
  299. PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
  300. PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
  301. PCI: 00:02.0 20 * [0x0 - 0x3f] io
  302. PCI: 00:1f.2 20 * [0x40 - 0x5f] io
  303. PCI: 00:1f.2 10 * [0x60 - 0x67] io
  304. PCI: 00:1f.2 18 * [0x68 - 0x6f] io
  305. PCI: 00:1f.2 14 * [0x70 - 0x73] io
  306. PCI: 00:1f.2 1c * [0x74 - 0x77] io
  307. PCI_DOMAIN: 0000 compute_resources_io: base: 78 size: 78 align: 6 gran: 0 limit: ffff done
  308. PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
  309. PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  310. PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
  311. PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
  312. PCI: 01:00.0 10 * [0x0 - 0x7ffff] mem
  313. PCI: 01:00.0 30 * [0x80000 - 0x8ffff] mem
  314. PCI: 00:1c.0 compute_resources_mem: base: 90000 size: 100000 align: 20 gran: 20 limit: ffffffff done
  315. PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
  316. PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem
  317. PCI: 00:1c.0 20 * [0x10400000 - 0x104fffff] mem
  318. PCI: 00:1b.0 10 * [0x10500000 - 0x10503fff] mem
  319. PCI: 00:1f.6 10 * [0x10504000 - 0x10504fff] mem
  320. PCI: 00:1f.2 24 * [0x10505000 - 0x105057ff] mem
  321. PCI: 00:1a.0 10 * [0x10505800 - 0x10505bff] mem
  322. PCI: 00:1d.0 10 * [0x10505c00 - 0x10505fff] mem
  323. PCI: 00:1f.3 10 * [0x10506000 - 0x105060ff] mem
  324. PCI: 00:16.0 10 * [0x10506100 - 0x1050610f] mem
  325. PCI_DOMAIN: 0000 compute_resources_mem: base: 10506110 size: 10506110 align: 28 gran: 0 limit: ffffffff done
  326. avoid_fixed_resources: PCI_DOMAIN: 0000
  327. avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
  328. avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
  329. constrain_resources: PCI_DOMAIN: 0000
  330. constrain_resources: PCI: 00:00.0
  331. constrain_resources: PCI: 00:02.0
  332. constrain_resources: PCI: 00:16.0
  333. constrain_resources: PCI: 00:1a.0
  334. constrain_resources: PCI: 00:1b.0
  335. constrain_resources: PCI: 00:1c.0
  336. constrain_resources: PCI: 01:00.0
  337. constrain_resources: PCI: 00:1d.0
  338. constrain_resources: PCI: 00:1f.0
  339. constrain_resources: PNP: 00ff.1
  340. constrain_resources: PNP: 00ff.0
  341. constrain_resources: PCI: 00:1f.2
  342. constrain_resources: PCI: 00:1f.3
  343. constrain_resources: PCI: 00:1f.6
  344. avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
  345. lim->base 00001000 lim->limit 0000ffff
  346. avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff
  347. lim->base 00000000 lim->limit efffffff
  348. Setting resources...
  349. PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:78 align:6 gran:0 limit:ffff
  350. Assigned: PCI: 00:02.0 20 * [0x1000 - 0x103f] io
  351. Assigned: PCI: 00:1f.2 20 * [0x1040 - 0x105f] io
  352. Assigned: PCI: 00:1f.2 10 * [0x1060 - 0x1067] io
  353. Assigned: PCI: 00:1f.2 18 * [0x1068 - 0x106f] io
  354. Assigned: PCI: 00:1f.2 14 * [0x1070 - 0x1073] io
  355. Assigned: PCI: 00:1f.2 1c * [0x1074 - 0x1077] io
  356. PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1078 size: 78 align: 6 gran: 0 done
  357. PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
  358. PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
  359. PCI_DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:10506110 align:28 gran:0 limit:efffffff
  360. Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem
  361. Assigned: PCI: 00:02.0 10 * [0xe0000000 - 0xe03fffff] mem
  362. Assigned: PCI: 00:1c.0 20 * [0xe0400000 - 0xe04fffff] mem
  363. Assigned: PCI: 00:1b.0 10 * [0xe0500000 - 0xe0503fff] mem
  364. Assigned: PCI: 00:1f.6 10 * [0xe0504000 - 0xe0504fff] mem
  365. Assigned: PCI: 00:1f.2 24 * [0xe0505000 - 0xe05057ff] mem
  366. Assigned: PCI: 00:1a.0 10 * [0xe0505800 - 0xe0505bff] mem
  367. Assigned: PCI: 00:1d.0 10 * [0xe0505c00 - 0xe0505fff] mem
  368. Assigned: PCI: 00:1f.3 10 * [0xe0506000 - 0xe05060ff] mem
  369. Assigned: PCI: 00:16.0 10 * [0xe0506100 - 0xe050610f] mem
  370. PCI_DOMAIN: 0000 allocate_resources_mem: next_base: e0506110 size: 10506110 align: 28 gran: 0 done
  371. PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
  372. PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
  373. PCI: 00:1c.0 allocate_resources_mem: base:e0400000 size:100000 align:20 gran:20 limit:efffffff
  374. Assigned: PCI: 01:00.0 10 * [0xe0400000 - 0xe047ffff] mem
  375. Assigned: PCI: 01:00.0 30 * [0xe0480000 - 0xe048ffff] mem
  376. PCI: 00:1c.0 allocate_resources_mem: next_base: e0490000 size: 100000 align: 20 gran: 20 done
  377. Root Device assign_resources, bus 0 link: 0
  378. TOUUD 0x14f600000 TOLUD 0xafa00000 TOM 0x100000000
  379. MEBASE 0xff000000
  380. IGD decoded, subtracting 32M UMA and 2M GTT
  381. TSEG base 0xad000000 size 8M
  382. Available memory below 4GB: 2768M
  383. Available memory above 4GB: 1270M
  384. Adding UMA memory area base=0xad000000 size=0x2a00000
  385. Adding PCIe config bar base=0xf0000000 size=0x4000000
  386. PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
  387. PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig>
  388. PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64
  389. PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
  390. PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
  391. PCI: 00:16.0 10 <- [0x00e0506100 - 0x00e050610f] size 0x00000010 gran 0x04 mem64
  392. PCI: 00:1a.0 10 <- [0x00e0505800 - 0x00e0505bff] size 0x00000400 gran 0x0a mem
  393. PCI: 00:1b.0 10 <- [0x00e0500000 - 0x00e0503fff] size 0x00004000 gran 0x0e mem64
  394. PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
  395. PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
  396. PCI: 00:1c.0 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 01 mem
  397. PCI: 00:1c.0 assign_resources, bus 1 link: 0
  398. PCI: 01:00.0 10 <- [0x00e0400000 - 0x00e047ffff] size 0x00080000 gran 0x13 mem64
  399. PCI: 01:00.0 30 <- [0x00e0480000 - 0x00e048ffff] size 0x00010000 gran 0x10 romem
  400. PCI: 00:1c.0 assign_resources, bus 1 link: 0
  401. PCI: 00:1d.0 10 <- [0x00e0505c00 - 0x00e0505fff] size 0x00000400 gran 0x0a mem
  402. PCI: 00:1f.0 assign_resources, bus 0 link: 0
  403. PCI: 00:1f.0 assign_resources, bus 0 link: 0
  404. PCI: 00:1f.2 10 <- [0x0000001060 - 0x0000001067] size 0x00000008 gran 0x03 io
  405. PCI: 00:1f.2 14 <- [0x0000001070 - 0x0000001073] size 0x00000004 gran 0x02 io
  406. PCI: 00:1f.2 18 <- [0x0000001068 - 0x000000106f] size 0x00000008 gran 0x03 io
  407. PCI: 00:1f.2 1c <- [0x0000001074 - 0x0000001077] size 0x00000004 gran 0x02 io
  408. PCI: 00:1f.2 20 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io
  409. PCI: 00:1f.2 24 <- [0x00e0505000 - 0x00e05057ff] size 0x00000800 gran 0x0b mem
  410. PCI: 00:1f.3 10 <- [0x00e0506000 - 0x00e05060ff] size 0x00000100 gran 0x08 mem64
  411. PCI: 00:1f.6 10 <- [0x00e0504000 - 0x00e0504fff] size 0x00001000 gran 0x0c mem64
  412. PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
  413. Root Device assign_resources, bus 0 link: 0
  414. Done setting resources.
  415. Show resources in subtree (Root Device)...After assigning values.
  416. Root Device child on link 0 APIC_CLUSTER: 0
  417. APIC_CLUSTER: 0 child on link 0 APIC: 00
  418. APIC: 00
  419. APIC: acac
  420. PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  421. PCI_DOMAIN: 0000 resource base 1000 size 78 align 6 gran 0 limit ffff flags 40040100 index 10000000
  422. PCI_DOMAIN: 0000 resource base d0000000 size 10506110 align 28 gran 0 limit efffffff flags 40040200 index 10000100
  423. PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
  424. PCI_DOMAIN: 0000 resource base 100000 size acf00000 align 0 gran 0 limit 0 flags e0004200 index 4
  425. PCI_DOMAIN: 0000 resource base 100000000 size 4f600000 align 0 gran 0 limit 0 flags e0004200 index 5
  426. PCI_DOMAIN: 0000 resource base ad000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
  427. PCI_DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7
  428. PCI: 00:00.0
  429. PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
  430. PCI: 00:02.0
  431. PCI: 00:02.0 resource base e0000000 size 400000 align 22 gran 22 limit efffffff flags 60000201 index 10
  432. PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18
  433. PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit ffff flags 60000100 index 20
  434. PCI: 00:16.0
  435. PCI: 00:16.0 resource base e0506100 size 10 align 4 gran 4 limit efffffff flags 60000201 index 10
  436. PCI: 00:16.1
  437. PCI: 00:16.2
  438. PCI: 00:16.3
  439. PCI: 00:19.0
  440. PCI: 00:1a.0
  441. PCI: 00:1a.0 resource base e0505800 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
  442. PCI: 00:1b.0
  443. PCI: 00:1b.0 resource base e0500000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10
  444. PCI: 00:1c.2
  445. PCI: 00:1c.1
  446. PCI: 00:1c.0 child on link 0 PCI: 01:00.0
  447. PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
  448. PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
  449. PCI: 00:1c.0 resource base e0400000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
  450. PCI: 01:00.0
  451. PCI: 01:00.0 resource base e0400000 size 80000 align 19 gran 19 limit efffffff flags 60000201 index 10
  452. PCI: 01:00.0 resource base e0480000 size 10000 align 16 gran 16 limit efffffff flags 60002200 index 30
  453. PCI: 00:1c.3
  454. PCI: 00:1c.4
  455. PCI: 00:1c.5
  456. PCI: 00:1c.6
  457. PCI: 00:1c.7
  458. PCI: 00:1d.0
  459. PCI: 00:1d.0 resource base e0505c00 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
  460. PCI: 00:1e.0
  461. PCI: 00:1f.0 child on link 0 PNP: 00ff.1
  462. PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
  463. PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
  464. PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
  465. PNP: 00ff.1
  466. PNP: 00ff.0
  467. PCI: 00:1f.2
  468. PCI: 00:1f.2 resource base 1060 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
  469. PCI: 00:1f.2 resource base 1070 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
  470. PCI: 00:1f.2 resource base 1068 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
  471. PCI: 00:1f.2 resource base 1074 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
  472. PCI: 00:1f.2 resource base 1040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
  473. PCI: 00:1f.2 resource base e0505000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 24
  474. PCI: 00:1f.3
  475. PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
  476. PCI: 00:1f.3 resource base e0506000 size 100 align 8 gran 8 limit efffffff flags 60000201 index 10
  477. PCI: 00:1f.5
  478. PCI: 00:1f.6
  479. PCI: 00:1f.6 resource base e0504000 size 1000 align 12 gran 12 limit efffffff flags 60000201 index 10
  480. Done allocating resources.
  481. Enabling resources...
  482. PCI: 00:00.0 subsystem <- 1ae0/c000
  483. PCI: 00:00.0 cmd <- 06
  484. PCI: 00:02.0 subsystem <- 1ae0/c000
  485. PCI: 00:02.0 cmd <- 03
  486. PCI: 00:16.0 subsystem <- 1ae0/c000
  487. PCI: 00:16.0 cmd <- 02
  488. PCI: 00:1a.0 subsystem <- 1ae0/c000
  489. PCI: 00:1a.0 cmd <- 102
  490. PCI: 00:1b.0 subsystem <- 1ae0/c000
  491. PCI: 00:1b.0 cmd <- 102
  492. PCI: 00:1c.0 bridge ctrl <- 0003
  493. PCI: 00:1c.0 subsystem <- 1ae0/c000
  494. PCI: 00:1c.0 cmd <- 106
  495. PCI: 00:1d.0 subsystem <- 1ae0/c000
  496. PCI: 00:1d.0 cmd <- 102
  497. pch_decode_init
  498. PCI: 00:1f.0 subsystem <- 1ae0/c000
  499. PCI: 00:1f.0 cmd <- 107
  500. PCI: 00:1f.2 subsystem <- 1ae0/c000
  501. PCI: 00:1f.2 cmd <- 03
  502. PCI: 00:1f.3 subsystem <- 1ae0/c000
  503. PCI: 00:1f.3 cmd <- 103
  504. PCI: 00:1f.6 subsystem <- 1ae0/c000
  505. PCI: 00:1f.6 cmd <- 02
  506. PCI: 01:00.0 cmd <- 02
  507. done.
  508. Initializing devices...
  509. Root Device init
  510. link_ec_init
  511. SF: Detected W25Q64 with page size 1000, total 800000
  512. FMAP: Found "FMAP" version 1.0 at ffe10000.
  513. FMAP: base = 0 size = 800000 #areas = 30
  514. FMAP: area RW_ELOG found
  515. FMAP: offset: 3f0000
  516. FMAP: size: 16384 bytes
  517. FMAP: No valid base address, using 0xff800000
  518. FMAP: RW_ELOG at ffbf0000 (offset 3f0000)
  519. ELOG: MEM @0x00157ad8 FLASH @0x00156ad8 [SPI 0x003f0000]
  520. ELOG: areas are 4096 bytes, full threshold 3072, shrink size 1024
  521. ELOG: Event(17) added with size 13
  522. SF: Winbond: Successfully programmed 13 bytes @ 0x3f0bd1
  523. ELOG: Event(91) added with size 10
  524. SF: Winbond: Successfully programmed 10 bytes @ 0x3f0bde
  525. Chrome EC: Set WAKE mask to 0x00000000
  526. APIC_CLUSTER: 0 init
  527. start_eip=0x0000a000, offset=0x00100000, code_size=0x00000062
  528. ELOG: Event(93) added with size 9
  529. SF: Winbond: Successfully programmed 9 bytes @ 0x3f0be8
  530. ELOG: Event(9A) added with size 9
  531. SF: Winbond: Successfully programmed 9 bytes @ 0x3f0bf1
  532. ELOG: Event(9E) added with size 10
  533. SF: Winbond: Successfully programmed 10 bytes @ 0x3f0bfa
  534. Installing SMM handler to 0xad000000
  535. Installing IED header to 0xad400000
  536. Initializing SMM handler... ... pmbase = 0x0500
  537.  
  538. SMI_STS: MCSMI PM1
  539. PM1_STS: WAK PWRBTN BM
  540. GPE0_STS:
  541. ALT_GP_SMI_STS:
  542. TCO_STS:
  543. ... raise SMI#
  544. Initializing CPU #0
  545. CPU: vendor Intel device 306a9
  546. CPU: family 06, model 3a, stepping 09
  547. Enabling cache
  548. CBFS: Looking for 'microcode_blob.bin'
  549. CBFS: found.
  550. microcode: sig=0x306a9 pf=0x10 revision=0x12
  551. microcode: updated to revision 0x12 date=2012-04-12
  552. CPU: Intel(R) Core(TM) i5-3427U CPU @ 1.80GHz.
  553.  
  554. Setting fixed MTRRs(0-88) Type: UC
  555. Setting fixed MTRRs(0-16) Type: WB
  556. DONE fixed MTRRs
  557. call enable_fixed_mtrr()
  558. Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
  559. Setting variable MTRR 1, base: 2048MB, range: 512MB, type WB
  560. Setting variable MTRR 2, base: 2560MB, range: 256MB, type WB
  561. Adding hole at 2768MB-2816MB
  562. Setting variable MTRR 3, base: 2768MB, range: 16MB, type UC
  563. Setting variable MTRR 4, base: 2784MB, range: 32MB, type UC
  564. Zero-sized MTRR range @0KB
  565. Allocate an msr - basek = 00400000, sizek = 0013d800,
  566. Setting variable MTRR 5, base: 4096MB, range: 1024MB, type WB
  567. Setting variable MTRR 6, base: 5120MB, range: 256MB, type WB
  568. Adding hole at 5366MB-5376MB
  569. Setting variable MTRR 7, base: 5366MB, range: 2MB, type UC
  570. Running out of variable MTRRs!
  571. Zero-sized MTRR range @0KB
  572. DONE variable MTRRs
  573. Clear out the extra MTRR's
  574. call enable_var_mtrr()
  575. Leave x86_setup_var_mtrrs
  576.  
  577. MTRR check
  578. Fixed MTRRs : Enabled
  579. Variable MTRRs: Enabled
  580.  
  581. Setting up local apic... apic_id: 0x00 done.
  582. model_x06ax: energy policy set to 6
  583. model_x06ax: frequency set to 1800
  584. Turbo is available but hidden
  585. Turbo has been enabled
  586. CPU: 0 has 2 cores, 2 threads per core
  587. CPU: 0 has core 1
  588. CPU1: stack_base 00154000, stack_end 00154ff8
  589. Asserting INIT.
  590. Waiting for send to finish...
  591. +Deasserting INIT.
  592. Waiting for send to finish...
  593. +#startup loops: 2.
  594. Sending STARTUP #1 to 1.
  595. After apic_write.
  596. Initializing CPU #1
  597. Startup point 1.
  598. CPU: vendor Intel device 306a9
  599. Waiting for send to finish...
  600. CPU: family 06, model 3a, stepping 09
  601. +Enabling cache
  602. Sending STARTUP #2 to 1.
  603. After apic_write.
  604. CBFS: Looking for 'microcode_blob.bin'
  605. CBFS: found.
  606. microcode: sig=0x306a9 pf=0x10 revision=0x12
  607. Startup point 1.
  608. Waiting for send to finish...
  609. +After Startup.
  610. microcode: updated to revision 0x12 date=2012-04-12
  611. CPU: 0 has core 2
  612. CPU2: stack_base 00153000, stack_end 00153ff8
  613. CPU: Intel(R) Core(TM) i5-3427U CPU @ 1.80GHz.
  614.  
  615. Setting fixed MTRRs(0-88) Type: UC
  616. Asserting INIT.
  617. Waiting for send to finish...
  618. +Deasserting INIT.
  619. Waiting for send to finish...
  620. +#startup loops: 2.
  621. Sending STARTUP #1 to 2.
  622. After apic_write.
  623. Initializing CPU #2
  624. CPU: vendor Intel device 306a9
  625. Startup point 1.
  626. Waiting for send to finish...
  627. +Setting fixed MTRRs(0-16) Type: WB
  628. CPU: family 06, model 3a, stepping 09
  629. Enabling cache
  630. Sending STARTUP #2 to 2.
  631. After apic_write.
  632. CBFS: Looking for 'microcode_blob.bin'
  633. CBFS: found.
  634. microcode: sig=0x306a9 pf=0x10 revision=0x0
  635. Startup point 1.
  636. Waiting for send to finish...
  637. +DONE fixed MTRRs
  638. call enable_fixed_mtrr()
  639. Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
  640. After Startup.
  641. CPU: 0 has core 3
  642. CPU3: stack_base 00152000, stack_end 00152ff8
  643. Asserting INIT.
  644. Waiting for send to finish...
  645. +Setting variable MTRR 1, base: 2048MB, range: 512MB, type WB
  646. Setting variable MTRR 2, base: 2560MB, range: 256MB, type WB
  647. microcode: updated to revision 0x12 date=2012-04-12
  648. Adding hole at 2768MB-2816MB
  649. Setting variable MTRR 3, base: 2768MB, range: 16MB, type UC
  650. CPU: Intel(R) Core(TM) i5-3427U CPU @ 1.80GHz.
  651.  
  652. Setting fixed MTRRs(0-88) Type: UC
  653. Setting variable MTRR 4, base: 2784MB, range: 32MB, type UC
  654. Zero-sized MTRR range @0KB
  655. Allocate an msr - basek = 00400000, sizek = 0013d800,
  656. Setting variable MTRR 5, base: 4096MB, range: 1024MB, type WB
  657. Setting variable MTRR 6, base: 5120MB, range: 256MB, type WB
  658. Adding hole at 5366MB-5376MB
  659. Setting variable MTRR 7, base: 5366MB, range: 2MB, type UC
  660. Running out of variable MTRRs!
  661. Zero-sized MTRR range @0KB
  662. DONE variable MTRRs
  663. Clear out the extra MTRR's
  664. Deasserting INIT.
  665. Waiting for send to finish...
  666. +#startup loops: 2.
  667. Sending STARTUP #1 to 3.
  668. After apic_write.
  669. Initializing CPU #3
  670. call enable_var_mtrr()
  671. Startup point 1.
  672. Waiting for send to finish...
  673. +Leave x86_setup_var_mtrrs
  674. Setting fixed MTRRs(0-16) Type: WB
  675. Sending STARTUP #2 to 3.
  676.  
  677. MTRR check
  678. Fixed MTRRs : Enabled
  679. Variable MTRRs: Enabled
  680.  
  681. CPU: vendor Intel device 306a9
  682. After apic_write.
  683. Setting up local apic...DONE fixed MTRRs
  684. apic_id: 0x01 done.
  685. Startup point 1.
  686. Waiting for send to finish...
  687. +call enable_fixed_mtrr()
  688. model_x06ax: energy policy set to 6
  689. After Startup.
  690. CPU #0 initialized
  691. Waiting for 3 CPUS to stop
  692. model_x06ax: frequency set to 1800
  693. CPU #1 initialized
  694. CPU: family 06, model 3a, stepping 09
  695. Waiting for 2 CPUS to stop
  696. Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
  697. Enabling cache
  698. Setting variable MTRR 1, base: 2048MB, range: 512MB, type WB
  699. CBFS: Looking for 'microcode_blob.bin'
  700. CBFS: found.
  701. microcode: sig=0x306a9 pf=0x10 revision=0x12
  702. microcode: updated to revision 0x12 date=2012-04-12
  703. Setting variable MTRR 2, base: 2560MB, range: 256MB, type WB
  704. CPU: Intel(R) Core(TM) i5-3427U CPU @ 1.80GHz.
  705.  
  706. Setting fixed MTRRs(0-88) Type: UC
  707. Adding hole at 2768MB-2816MB
  708. Setting variable MTRR 3, base: 2768MB, range: 16MB, type UC
  709. Setting variable MTRR 4, base: 2784MB, range: 32MB, type UC
  710. Zero-sized MTRR range @0KB
  711. Allocate an msr - basek = 00400000, sizek = 0013d800,
  712. Setting variable MTRR 5, base: 4096MB, range: 1024MB, type WB
  713. Setting variable MTRR 6, base: 5120MB, range: 256MB, type WB
  714. Adding hole at 5366MB-5376MB
  715. Setting variable MTRR 7, base: 5366MB, range: 2MB, type UC
  716. Running out of variable MTRRs!
  717. Zero-sized MTRR range @0KB
  718. DONE variable MTRRs
  719. Clear out the extra MTRR's
  720. call enable_var_mtrr()
  721. Leave x86_setup_var_mtrrs
  722.  
  723. MTRR check
  724. Fixed MTRRs : Enabled
  725. Variable MTRRs: Enabled
  726.  
  727. Setting up local apic... apic_id: 0x02 done.
  728. Setting fixed MTRRs(0-16) Type: WB
  729. model_x06ax: energy policy set to 6
  730. model_x06ax: frequency set to 1800
  731. CPU #2 initialized
  732. Waiting for 1 CPUS to stop
  733. DONE fixed MTRRs
  734. call enable_fixed_mtrr()
  735. Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
  736. Setting variable MTRR 1, base: 2048MB, range: 512MB, type WB
  737. Setting variable MTRR 2, base: 2560MB, range: 256MB, type WB
  738. Adding hole at 2768MB-2816MB
  739. Setting variable MTRR 3, base: 2768MB, range: 16MB, type UC
  740. Setting variable MTRR 4, base: 2784MB, range: 32MB, type UC
  741. Zero-sized MTRR range @0KB
  742. Allocate an msr - basek = 00400000, sizek = 0013d800,
  743. Setting variable MTRR 5, base: 4096MB, range: 1024MB, type WB
  744. Setting variable MTRR 6, base: 5120MB, range: 256MB, type WB
  745. Adding hole at 5366MB-5376MB
  746. Setting variable MTRR 7, base: 5366MB, range: 2MB, type UC
  747. Running out of variable MTRRs!
  748. Zero-sized MTRR range @0KB
  749. DONE variable MTRRs
  750. Clear out the extra MTRR's
  751. call enable_var_mtrr()
  752. Leave x86_setup_var_mtrrs
  753.  
  754. MTRR check
  755. Fixed MTRRs : Enabled
  756. Variable MTRRs: Enabled
  757.  
  758. Setting up local apic... apic_id: 0x03 done.
  759. model_x06ax: energy policy set to 6
  760. model_x06ax: frequency set to 1800
  761. CPU #3 initialized
  762. All AP CPUs stopped (5050 loops)
  763. CPU1: stack: 00154000 - 00155000, lowest used address 00154c8c, stack used: 884 bytes
  764. CPU2: stack: 00153000 - 00154000, lowest used address 00153c8c, stack used: 884 bytes
  765. CPU3: stack: 00152000 - 00153000, lowest used address 00152c8c, stack used: 884 bytes
  766. PCI: 00:00.0 init
  767. Set BIOS_RESET_CPL
  768. CPU TDP: 17 Watts
  769. PCI: 00:02.0 init
  770. GT Power Management Init
  771. IVB GT2 17W Power Meter Weights
  772. CBFS: Looking for 'pci8086,0166.rom'
  773. CBFS: found.
  774. In CBFS, ROM address for PCI: 00:02.0 = fff0fd78
  775. PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040
  776. PCI ROM image, vendor ID 8086, device ID 0106,
  777. PCI ROM image, Class Code 030000, Code Type 00
  778. Copying VGA ROM Image from fff0fd78 to 0xc0000, 0x10000 bytes
  779. Real mode stub @00000600: 867 bytes
  780. Calling Option ROM...
  781. int15_handler: INT15 function 5fac!
  782. ... Option ROM returned.
  783. VBE: Getting information about VESA mode 4164
  784. VBE: resolution: 1280x850@16
  785. VBE: framebuffer: d0000000
  786. VBE: Setting VESA mode 4164
  787. VGA Option ROM has been loaded
  788. GT Power Management Init (post VBIOS)
  789. PCI: 00:16.0 init
  790. ME: FW Partition Table : OK
  791. ME: Bringup Loader Failure : NO
  792. ME: Firmware Init Complete : YES
  793. ME: Manufacturing Mode : NO
  794. ME: Boot Options Present : NO
  795. ME: Update In Progress : NO
  796. ME: Current Working State : Normal
  797. ME: Current Operation State : M0 with UMA
  798. ME: Current Operation Mode : Normal
  799. ME: Error Code : No Error
  800. ME: Progress Phase : Host Communication
  801. ME: Power Management Event : Pseudo-global reset
  802. ME: Progress Phase State : Host communication established
  803. ME: BIOS path: Normal
  804. ME: Extend SHA-256: 9e40dedefae0d58db5505087b9fbf6131b56fb5f404e3b7f7e87d5e3c7f539e4
  805. ME: MBP item header 00020103
  806. ME: MBP item header 00050102
  807. ME: MBP item header 00020501
  808. ME: MBP item header 00020201
  809. ME: MBP item header 02030101
  810. ME: MBP item header 02060301
  811. ME: MBP item header 02090401
  812. ME: mbp read OK after 1 cycles
  813. ME: found version 8.0.20.1513
  814. ME Capability: Full Network manageability : disabled
  815. ME Capability: Regular Network manageability : disabled
  816. ME Capability: Manageability : disabled
  817. ME Capability: Small business technology : disabled
  818. ME Capability: Level III manageability : disabled
  819. ME Capability: IntelR Anti-Theft (AT) : disabled
  820. ME Capability: IntelR Capability Licensing Service (CLS) : enabled
  821. ME Capability: IntelR Power Sharing Technology (MPC) : enabled
  822. ME Capability: ICC Over Clocking : enabled
  823. ME Capability: Protected Audio Video Path (PAVP) : disabled
  824. ME Capability: IPV6 : disabled
  825. ME Capability: KVM Remote Control (KVM) : disabled
  826. ME Capability: Outbreak Containment Heuristic (OCH) : disabled
  827. ME Capability: Virtual LAN (VLAN) : enabled
  828. ME Capability: TLS : disabled
  829. ME Capability: Wireless LAN (WLAN) : disabled
  830. PCI: 00:1a.0 init
  831. EHCI: Setting up controller.. done.
  832. PCI: 00:1b.0 init
  833. Azalia: base = e0500000
  834. Azalia: codec_mask = 09
  835. Azalia: Initializing codec #3
  836. Azalia: codec viddid: 80862806
  837. Azalia: verb_size: 16
  838. Azalia: verb loaded.
  839. Azalia: Initializing codec #0
  840. Azalia: codec viddid: 11020011
  841. Azalia: verb_size: 80
  842. Azalia: verb loaded.
  843. PCI: 00:1c.0 init
  844. Initializing PCH PCIe bridge.
  845. PCI: 00:1d.0 init
  846. EHCI: Setting up controller.. done.
  847. PCI: 00:1f.0 init
  848. pch: lpc_init
  849. Southbridge APIC ID = 2
  850. Dumping IOAPIC registers
  851. reg 0x0000: 0x02000000
  852. reg 0x0001: 0x00170020
  853. reg 0x0002: 0x00170020
  854. Set power off after power failure.
  855. NMI sources disabled.
  856. PantherPoint PM init
  857. rtc_failed = 0x0
  858. RTC Init
  859. i8259_configure_irq_trigger: current interrupts are 0x0
  860. i8259_configure_irq_trigger: try to set interrupts 0x200
  861. Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
  862. done.
  863. Locking SMM.
  864. PCI: 00:1f.2 init
  865. SATA: Initializing...
  866. SATA: Controller in AHCI mode.
  867. ABAR: E0505000
  868. PCI: 00:1f.3 init
  869. PCI: 00:1f.6 init
  870. PCI: 01:00.0 init
  871. PNP: 00ff.0 init
  872. Google Chrome EC: Initializing keyboard.
  873. Keyboard init...
  874. Google Chrome EC: Hello got back 11223344 status (0)
  875. Google Chrome EC: version:
  876. ro: link_v1.2.120-1137a99
  877. rw: link_v1.2.138-e4a9915
  878. running image: 2
  879. Devices initialized
  880. Show all devs...After init.
  881. Root Device: enabled 1
  882. APIC_CLUSTER: 0: enabled 1
  883. APIC: 00: enabled 1
  884. APIC: acac: enabled 0
  885. PCI_DOMAIN: 0000: enabled 1
  886. PCI: 00:00.0: enabled 1
  887. PCI: 00:02.0: enabled 1
  888. PCI: 00:16.0: enabled 1
  889. PCI: 00:16.1: enabled 0
  890. PCI: 00:16.2: enabled 0
  891. PCI: 00:16.3: enabled 0
  892. PCI: 00:19.0: enabled 0
  893. PCI: 00:1a.0: enabled 1
  894. PCI: 00:1b.0: enabled 1
  895. PCI: 00:1c.2: enabled 0
  896. PCI: 00:1c.1: enabled 0
  897. PCI: 00:1c.0: enabled 1
  898. PCI: 00:1c.3: enabled 0
  899. PCI: 00:1c.4: enabled 0
  900. PCI: 00:1c.5: enabled 0
  901. PCI: 00:1c.6: enabled 0
  902. PCI: 00:1c.7: enabled 0
  903. PCI: 00:1d.0: enabled 1
  904. PCI: 00:1e.0: enabled 0
  905. PCI: 00:1f.0: enabled 1
  906. PNP: 00ff.1: enabled 1
  907. PCI: 00:1f.2: enabled 1
  908. PCI: 00:1f.3: enabled 1
  909. PCI: 00:1f.5: enabled 0
  910. PCI: 00:1f.6: enabled 1
  911. PCI: 01:00.0: enabled 1
  912. PNP: 00ff.0: enabled 1
  913. APIC: 01: enabled 1
  914. APIC: 02: enabled 1
  915. APIC: 03: enabled 1
  916. Re-Initializing CBMEM area to 0xacec0000
  917. Adding CBMEM entry as no. 4
  918. Moving GDT to aced1000...ok
  919. Updating MRC cache data.
  920. FMAP: area RW_MRC_CACHE found
  921. FMAP: offset: 3e0000
  922. FMAP: size: 65536 bytes
  923. FMAP: No valid base address, using 0xff800000
  924. FMAP: RW_MRC_CACHE at ffbe0000 (offset 3e0000)
  925. find_current_mrc_cache_local: picked entry 1 from cache block
  926. MRC data in flash is up to date. No update.
  927. High Tables Base is acec0000.
  928. Adding CBMEM entry as no. 5
  929. ACPI: Writing ACPI tables at aced1200.
  930. ACPI: * FACS
  931. ACPI: * DSDT
  932. ACPI: * FADT
  933. ACPI: added table 1/32, length now 40
  934. ACPI: * HPET
  935. ACPI: added table 2/32, length now 44
  936. ACPI: * MADT
  937. ACPI: added table 3/32, length now 48
  938. ACPI: * MCFG
  939. ACPI: added table 4/32, length now 52
  940. ACPI: * IGD OpRegion
  941. GET_VBIOS: aa55 8086 0 0 3
  942. ... VBIOS found at 000c0000
  943. ACPI: * GNVS
  944. ACPI: Patching up global NVS in DSDT at offset 0x0254 -> 0xaced6c70
  945. Adding CBMEM entry as no. 6
  946. ELOG: Event(A0) added with size 9
  947. SF: Winbond: Successfully programmed 9 bytes @ 0x3f0c04
  948. SF: erase 20 3f 0 0 (3f1000)
  949. SF: Successfully erased 4096 bytes @ 0x3f0000
  950. SF: Winbond: Successfully programmed 8 bytes @ 0x3f0000
  951. SF: Winbond: Successfully programmed 2051 bytes @ 0x3f0008
  952. ELOG: Event(16) added with size 11
  953. SF: Winbond: Successfully programmed 11 bytes @ 0x3f080b
  954. ACPI: * DSDT @ aced1450 Length 3627
  955. ACPI: * SSDT
  956. Found 1 CPU(s) with 4 core(s) each.
  957. PSS: 1801MHz power 17000 control 0x1c00 status 0x1c00
  958. PSS: 1800MHz power 17000 control 0x1200 status 0x1200
  959. PSS: 1600MHz power 14748 control 0x1000 status 0x1000
  960. PSS: 1400MHz power 12601 control 0xe00 status 0xe00
  961. PSS: 1200MHz power 10552 control 0xc00 status 0xc00
  962. PSS: 1000MHz power 8595 control 0xa00 status 0xa00
  963. PSS: 800MHz power 6710 control 0x800 status 0x800
  964. PSS: 1801MHz power 17000 control 0x1c00 status 0x1c00
  965. PSS: 1800MHz power 17000 control 0x1200 status 0x1200
  966. PSS: 1600MHz power 14748 control 0x1000 status 0x1000
  967. PSS: 1400MHz power 12601 control 0xe00 status 0xe00
  968. PSS: 1200MHz power 10552 control 0xc00 status 0xc00
  969. PSS: 1000MHz power 8595 control 0xa00 status 0xa00
  970. PSS: 800MHz power 6710 control 0x800 status 0x800
  971. PSS: 1801MHz power 17000 control 0x1c00 status 0x1c00
  972. PSS: 1800MHz power 17000 control 0x1200 status 0x1200
  973. PSS: 1600MHz power 14748 control 0x1000 status 0x1000
  974. PSS: 1400MHz power 12601 control 0xe00 status 0xe00
  975. PSS: 1200MHz power 10552 control 0xc00 status 0xc00
  976. PSS: 1000MHz power 8595 control 0xa00 status 0xa00
  977. PSS: 800MHz power 6710 control 0x800 status 0x800
  978. PSS: 1801MHz power 17000 control 0x1c00 status 0x1c00
  979. PSS: 1800MHz power 17000 control 0x1200 status 0x1200
  980. PSS: 1600MHz power 14748 control 0x1000 status 0x1000
  981. PSS: 1400MHz power 12601 control 0xe00 status 0xe00
  982. PSS: 1200MHz power 10552 control 0xc00 status 0xc00
  983. PSS: 1000MHz power 8595 control 0xa00 status 0xa00
  984. PSS: 800MHz power 6710 control 0x800 status 0x800
  985. ACPI: added table 5/32, length now 56
  986. current = aced8df0
  987. ACPI: done.
  988. ACPI tables: 31728 bytes.
  989. Adding CBMEM entry as no. 7
  990. smbios_write_tables: acedc800
  991. Root Device (Google Link ChromeBook)
  992. APIC_CLUSTER: 0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
  993. APIC: 00 (Socket rPGA989 CPU)
  994. APIC: acac (Intel SandyBridge/IvyBridge CPU)
  995. PCI_DOMAIN: 0000 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
  996. PCI: 00:00.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
  997. PCI: 00:02.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
  998. PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  999. PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1000. PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1001. PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1002. PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1003. PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1004. PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1005. PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1006. PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1007. PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1008. PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1009. PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1010. PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1011. PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1012. PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1013. PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1014. PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1015. PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1016. PNP: 00ff.1 (Google Chrome EC)
  1017. PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1018. PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1019. PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1020. PCI: 00:1f.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
  1021. PCI: 01:00.0 ()
  1022. PNP: 00ff.0 ()
  1023. APIC: 01 ()
  1024. APIC: 02 ()
  1025. APIC: 03 ()
  1026. SMBIOS tables: 444 bytes.
  1027. Adding CBMEM entry as no. 8
  1028. Writing high table forward entry at 0x00000500
  1029. Wrote coreboot table at: 00000500, 0x10 bytes, checksum 82f0
  1030. New low_table_end: 0x00000528
  1031. Now going to write high coreboot table at 0xacedd000
  1032. rom_table_end = 0xacedd000
  1033. Adjust low_table_end from 0x00000528 to 0x00001000
  1034. Adjust rom_table_end from 0xacedd000 to 0xacee0000
  1035. Adding high table area
  1036. coreboot memory table:
  1037. 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  1038. 1. 0000000000001000-000000000009ffff: RAM
  1039. 2. 00000000000a0000-00000000000fffff: RESERVED
  1040. 3. 0000000000100000-0000000000efffff: RAM
  1041. 4. 0000000000f00000-0000000000ffffff: RESERVED
  1042. 5. 0000000001000000-000000001fffffff: RAM
  1043. 6. 0000000020000000-00000000201fffff: RESERVED
  1044. 7. 0000000020200000-000000003fffffff: RAM
  1045. 8. 0000000040000000-00000000401fffff: RESERVED
  1046. 9. 0000000040200000-00000000acebffff: RAM
  1047. 10. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
  1048. 11. 00000000ad000000-00000000af9fffff: RESERVED
  1049. 12. 00000000f0000000-00000000f3ffffff: RESERVED
  1050. 13. 0000000100000000-000000014f5fffff: RAM
  1051. Wrote coreboot table at: acedd000, 0x3b8 bytes, checksum 9f9b
  1052. coreboot table: 976 bytes.
  1053. Adding CBMEM entry as no. 9
  1054. 0. FREE SPACE acfe5000 0001b000
  1055. 1. MRC DATA acec0200 00000c00
  1056. 2. TIME STAMP acec0e00 00000200
  1057. 3. CONSOLE acec1000 00010000
  1058. 4. GDT aced1000 00000200
  1059. 5. ACPI aced1200 0000b400
  1060. 6. ACPI GNVS acedc600 00000200
  1061. 7. SMBIOS acedc800 00000800
  1062. 8. COREBOOT acedd000 00008000
  1063. 9. ACPI RESUMEacee5000 00100000
  1064. CBFS: Looking for 'fallback/payload'
  1065. CBFS: found.
  1066. Loading segment from rom address 0xfff3c878
  1067. code (compression=1)
  1068. New segment dstaddr 0x1110000 memsize 0x55c50 srcaddr 0xfff3c8cc filesize 0x1c0b5
  1069. (cleaned up) New segment addr 0x1110000 size 0x55c50 offset 0xfff3c8cc filesize 0x1c0b5
  1070. Loading segment from rom address 0xfff3c894
  1071. data (compression=1)
  1072. New segment dstaddr 0x1165c50 memsize 0x89c0 srcaddr 0xfff58981 filesize 0x1120
  1073. (cleaned up) New segment addr 0x1165c50 size 0x89c0 offset 0xfff58981 filesize 0x1120
  1074. Loading segment from rom address 0xfff3c8b0
  1075. Entry Point 0x00000000
  1076. Loading Segment: addr: 0x0000000001110000 memsz: 0x0000000000055c50 filesz: 0x000000000001c0b5
  1077. lb: [0x0000000000100000, 0x000000000015a000)
  1078. Post relocation: addr: 0x0000000001110000 memsz: 0x0000000000055c50 filesz: 0x000000000001c0b5
  1079. using LZMA
  1080. [ 0x01110000, 01150588, 0x01165c50) <- fff3c8cc
  1081. Clearing Segment: addr: 0x0000000001150588 memsz: 0x00000000000156c8
  1082. dest 01110000, end 01165c50, bouncebuffer ace0c000
  1083. Loading Segment: addr: 0x0000000001165c50 memsz: 0x00000000000089c0 filesz: 0x0000000000001120
  1084. lb: [0x0000000000100000, 0x000000000015a000)
  1085. Post relocation: addr: 0x0000000001165c50 memsz: 0x00000000000089c0 filesz: 0x0000000000001120
  1086. using LZMA
  1087. [ 0x01165c50, 0116e610, 0x0116e610) <- fff58981
  1088. dest 01165c50, end 0116e610, bouncebuffer ace0c000
  1089. Loaded segments
  1090. PCH watchdog disabled
  1091. Jumping to boot code at 1110008
  1092. CPU0: stack: 00155000 - 00156000, lowest used address 00155b1c, stack used: 1252 bytes
  1093. entry = 0x01110008
  1094. lb_start = 0x00100000
  1095. lb_size = 0x0005a000
  1096. adjust = 0xacd66000
  1097. buffer = 0xace0c000
  1098. elf_boot_notes = 0x0013f61c
  1099. adjusted_boot_notes = 0xacea561c
  1100. SCSI: Target spinup took 1 ms.
  1101. SATA link 1 timeout.
  1102. AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x1 impl SATA mode
  1103. flags: 64bit ncq ilck stag pm led clo pio slum part apst
  1104. scanning bus for devices...
  1105. Device 0: (0:0) Vendor: ATA Prod.: SanDisk SSD i100 Rev: 11.5
  1106. Type: Hard Disk
  1107. Capacity: 30533.8 MB = 29.8 GB (62533296 x 512)
  1108. Found 1 device(s).
  1109. intel_ich6_gpio.c: gpio_init: Found 8086:1e5d
  1110. vboot_flag_debug.c: vboot_flag_dump: vboot-flag-write-protect: port= 57, active_high=1, value=1
  1111. vboot_flag_debug.c: vboot_flag_dump: vboot-flag-recovery : port= -1, active_high=1, value=0
  1112. vboot_flag_debug.c: vboot_flag_dump: vboot-flag-developer : port= -1, active_high=1, value=0
  1113. vboot_flag_debug.c: vboot_flag_dump: vboot-flag-oprom-loaded : port= -1, active_high=1, value=1
  1114. cmd_vboot_twostop.c: twostop_init: FDT says oprom-matters
  1115. cros_fdtdec.c: process_fmap_node: Node 'rw-a': bad block-offset
  1116. cros_fdtdec.c: process_fmap_node: Node 'rw-b': bad block-offset
  1117. fmap.c: dump_fmap_entry: fmap 00610000:00000800
  1118. fmap.c: dump_fmap_entry: gbb 00611000:000ef000
  1119. fmap.c: dump_fmap_entry: firmware_id 00610800:00000040
  1120. fmap.c: dump_fmap_firmware_entry: rw-a
  1121. fmap.c: dump_fmap_entry: all 00200000:000f0000
  1122. fmap.c: dump_fmap_entry: boot 00210000:000dffc0
  1123. fmap.c: dump_fmap_entry: vblock 00200000:00010000
  1124. fmap.c: dump_fmap_entry: firmware_id 002effc0:00000040
  1125. fmap.c: dump_fmap_firmware_entry: block_offset ffffffffffffffff
  1126. fmap.c: dump_fmap_firmware_entry: rw-b
  1127. fmap.c: dump_fmap_entry: all 002f0000:000f0000
  1128. fmap.c: dump_fmap_entry: boot 00300000:000dffc0
  1129. fmap.c: dump_fmap_entry: vblock 002f0000:00010000
  1130. fmap.c: dump_fmap_entry: firmware_id 003dffc0:00000040
  1131. fmap.c: dump_fmap_firmware_entry: block_offset ffffffffffffffff
  1132. SF: Detected W25Q64 with page size 4 KiB, total 8 MiB
  1133. cmd_vboot_twostop.c: twostop_init: read-only firmware id: "Google_Link.2695.1.133"
  1134. cmd_vboot_twostop.c: twostop_init: hardware id: "LINK WISTERIA BGZ-K 3255"
  1135. crossystem_data.c: crossystem_data_init: crossystem data at 01100000
  1136. cmd_vboot_twostop.c: twostop_init_cparams: cparams:
  1137. cmd_vboot_twostop.c: twostop_init_cparams: - gbb_data : ffe11000
  1138. cmd_vboot_twostop.c: twostop_init_cparams: - gbb_size : 000ef000
  1139. cmd_vboot_twostop.c: twostop_init_cparams: - shared_data_blob : aced6f0a
  1140. cmd_vboot_twostop.c: twostop_init_cparams: - shared_data_size : 00000c00
  1141. cmd_vboot_twostop.c: check_ro_normal_support: twostop-optional
  1142. cmd_vboot_twostop.c: twostop_init_vboot_library: iparams.flags: 000003e4
  1143. Found TPM SLB9635 TT 1.2 by Infineon
  1144. cmd_vboot_twostop.c: twostop_init_vboot_library: iparams.out_flags: 000000ce
  1145. cmd_vboot_twostop.c: twostop_init_vboot_library: cdata->boot_developer_switch=1
  1146. memory_wipe.c: memory_wipe_execute: Wipe memory regions:
  1147. memory_wipe.c: memory_wipe_execute: [0x00000000001000, 0x000000000a0000)
  1148. memory_wipe.c: memory_wipe_execute: [0x00000000100000, 0x00000000f00000)
  1149. memory_wipe.c: memory_wipe_execute: [0x00000001000000, 0x00000001100000)
  1150. memory_wipe.c: memory_wipe_execute: [0x00000001104400, 0x00000020000000)
  1151. memory_wipe.c: memory_wipe_execute: [0x00000020200000, 0x00000040000000)
  1152. memory_wipe.c: memory_wipe_execute: [0x00000040200000, 0x000000abe699ec)
  1153. memory_wipe.c: memory_wipe_execute: [0x000000acebfc50, 0x000000acec0000)
  1154. memory_wipe.c: memory_wipe_execute: [0x00000100000000, 0x0000014f600000)
  1155. cmd_vboot_twostop.c: twostop_make_selection: selected_firmware: 1
  1156. cmd_vboot_twostop.c: twostop_select_and_set_main_firmware: selection: TWOSTOP_SELECT_FIRMWARE_A
  1157. cmd_vboot_twostop.c: twostop_select_and_set_main_firmware: active main firmware type : 2
  1158. cmd_vboot_twostop.c: twostop_select_and_set_main_firmware: active main firmware id : "Google_Link.2695.1.156"
  1159. cmd_vboot_twostop.c: twostop_boot: selection of bootstub: TWOSTOP_SELECT_FIRMWARE_A
  1160. cmd_vboot_twostop.c: twostop_jump: jump to readwrite main firmware at 0x1110000, size 0x60b80
  1161. SCSI: Target spinup took 1 ms.
  1162. SATA link 1 timeout.
  1163. AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x1 impl SATA mode
  1164. flags: 64bit ncq ilck stag pm led clo pio slum part apst
  1165. scanning bus for devices...
  1166. Device 0: (0:0) Vendor: ATA Prod.: SanDisk SSD i100 Rev: 11.5
  1167. Type: Hard Disk
  1168. Capacity: 30533.8 MB = 29.8 GB (62533296 x 512)
  1169. Found 1 device(s).
  1170. intel_ich6_gpio.c: gpio_init: Found 8086:1e5d
  1171. cros_fdtdec.c: process_fmap_node: Node 'rw-a': bad block-offset
  1172. cros_fdtdec.c: process_fmap_node: Node 'rw-b': bad block-offset
  1173. fmap.c: dump_fmap_entry: fmap 00610000:00000800
  1174. fmap.c: dump_fmap_entry: gbb 00611000:000ef000
  1175. fmap.c: dump_fmap_entry: firmware_id 00610800:00000040
  1176. fmap.c: dump_fmap_firmware_entry: rw-a
  1177. fmap.c: dump_fmap_entry: all 00200000:000f0000
  1178. fmap.c: dump_fmap_entry: boot 00210000:000dffc0
  1179. fmap.c: dump_fmap_entry: vblock 00200000:00010000
  1180. fmap.c: dump_fmap_entry: firmware_id 002effc0:00000040
  1181. fmap.c: dump_fmap_firmware_entry: block_offset ffffffffffffffff
  1182. fmap.c: dump_fmap_firmware_entry: rw-b
  1183. fmap.c: dump_fmap_entry: all 002f0000:000f0000
  1184. fmap.c: dump_fmap_entry: boot 00300000:000dffc0
  1185. fmap.c: dump_fmap_entry: vblock 002f0000:00010000
  1186. fmap.c: dump_fmap_entry: firmware_id 003dffc0:00000040
  1187. fmap.c: dump_fmap_firmware_entry: block_offset ffffffffffffffff
  1188. Found TPM SLB9635 TT 1.2 by Infineon
  1189. cmd_vboot_twostop.c: twostop_init_cparams: cparams:
  1190. cmd_vboot_twostop.c: twostop_init_cparams: - gbb_data : ffe11000
  1191. cmd_vboot_twostop.c: twostop_init_cparams: - gbb_size : 000ef000
  1192. cmd_vboot_twostop.c: twostop_init_cparams: - shared_data_blob : aced6f0a
  1193. cmd_vboot_twostop.c: twostop_init_cparams: - shared_data_size : 00000c00
  1194. 2x Refresh already enabled in memory controller
  1195. MRC cache slot 1 @ ffbe1000
  1196. SF: Detected W25Q64 with page size 4 KiB, total 8 MiB
  1197. 2x Refresh already enabled in RW_MRC_CACHE
  1198. SPI flash protection: WPSW=1 SRP0=1
  1199. Enabled Protected Range on RW_MRC_CACHE region
  1200. cros_fdtdec.c: cros_fdtdec_alloc_region: failed to find kernel in /chromeos-config'
  1201. cmd_vboot_twostop.c: twostop_main_firmware: kparams:
  1202. cmd_vboot_twostop.c: twostop_main_firmware: - kernel_buffer: : (null)
  1203. cmd_vboot_twostop.c: twostop_main_firmware: - kernel_buffer_size: : 00000000
  1204. cros_fdtdec.c: process_fmap_node: Node 'rw-a': bad block-offset
  1205. cros_fdtdec.c: process_fmap_node: Node 'rw-b': bad block-offset
  1206. SF: Detected W25Q64 with page size 4 KiB, total 8 MiB
  1207. ec.c: VbExEcGetExpectedRW: EC-RW image offset 2558848 size 77692.
  1208. size type name
  1209. ------------------------------------------
  1210. 44282 payload payload
  1211. 65536 option rom pci8086,0166.rom
  1212. 117 raw bootorder
  1213. 8 raw boot-menu-wait
  1214. 1986808 null (empty)
  1215.  
  1216. 5 file(s)
  1217.  
  1218. CODE/DATA: dst=000ea01c dst_len=90084 src=ffc00060 src_len=44226
  1219. Finalizing Coreboot
  1220. GNU GRUB version 2.02~beta2
  1221.  
  1222.  
  1223. +----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted.
  1224.  
  1225. Press enter to boot the selected OS, `e' to edit the commands
  1226.  
  1227. before booting or `c' for a command-line.
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