library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_alu is
end tb_alu;

architecture tb_Behavioral of tb_alu is
component alu

port (
        argA : in std_logic_vector(7 downto 0);
        argB : in std_logic_vector(7 downto 0);
        sel : in std_logic_vector (3 downto 0);
        result : out std_logic_vector(7 downto 0);
        F : out std_logic_vector(3 downto 0)
        );

end component;

    signal targA, targB, tresult: std_logic_vector(7 downto 0);
    signal tsel, tF: std_logic_vector (3 downto 0);
    signal tclk, treset: std_logic;
    signal toutput: std_logic_vector (11 downto 0);
begin

U1: alu port map(targA, targB, tresult, tsel, tF);




/*
targA <= "01010101";
targB <= "10101010";

tsel <= "0000", "0001" after 10 ps, "0010" after 20 ps, "0011" after 30 ps,
 "0100" after 40 ps, "0101" after 50 ps, "0110" after 60 ps, "0111" after 70 ps,
 "1000" after 80 ps; "1001" after 90 ps, "1010" after 100 ps, "1011" after 110 ps,
 "1100" after 120 ps, "1101" after 130 ps, "1110" after 140 ps, "1111" after 150 ps;
*/

 process
 begin
    tclk<= '0';
    wait for 5 ps;
    tclk <= not tclk;
    wait for 5 ps;
 end process;



end tb_Behavioral