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- C:\USRP2_fpga_NEMO\usrp2\top\USRP2>make
- C:/USRP2_fpga_NEMO/usrp2/top/USRP2/build/u2_rev3.xise
- xtclsh C:/USRP2_fpga_NEMO/usrp2/top/tcl/ise_helper.tcl ""
- >>> Creating project: C:/USRP2_fpga_NEMO/usrp2/top/USRP2/build/u2_rev3.xise
- Changed current working directory to the project directory:
- "C:/USRP2_fpga_NEMO/usrp2/top/USRP2/build"
- >>> Setting: Project[family] = Spartan3
- >>> Setting: Project[device] = xc3s2000
- >>> Setting: Project[package] = fg456
- >>> Setting: Project[speed] = -5
- >>> Setting: Project[top_level_module_type] = HDL
- >>> Setting: Project[synthesis_tool] = XST (VHDL/Verilog)
- >>> Setting: Project[simulator] = ISE Simulator (VHDL/Verilog)
- WARNING:TclTasksC - The value(s) of this property has been changed in the
- current release to "ISim (VHDL/Verilog)". The property value has been set to
- "ISim (VHDL/Verilog)". Please update your script to use the new value to
- avoid this message in the future.
- >>> Setting: Project[Preferred Language] = Verilog
- >>> Setting: Project[Enable Message Filtering] = FALSE
- >>> Setting: Project[Display Incremental Messages] = FALSE
- >>> Adding source to project: C:/USRP2_fpga_NEMO/usrp2/top/USRP2/u2_core.v
- INFO:HDLCompiler:1677 - Analyzing Verilog file
- \"C:/USRP2_fpga_NEMO/usrp2/top/USRP2/u2_core.v\" into library work
- INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
- >>> Adding source to project: C:/USRP2_fpga_NEMO/usrp2/top/USRP2/u2_rev3.v
- INFO:HDLCompiler:1677 - Analyzing Verilog file
- \"C:/USRP2_fpga_NEMO/usrp2/top/USRP2/u2_rev3.v\" into library work
- INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
- >>> Adding source to project: C:/USRP2_fpga_NEMO/usrp2/top/USRP2/u2_rev3.ucf
- >>> Adding source to project: )
- ERROR:TclTasksC:xfile_070: File(s) "./)" cannot be found
- while executing
- "xfile add $source"
- ("foreach" body line 3)
- invoked from within
- "foreach source $env(SOURCES) {
- puts ">>> Adding source to project: $source"
- xfile add $source
- }"
- invoked from within
- "if [file isfile $env(ISE_FILE)] {
- puts ">>> Opening project: $env(ISE_FILE)"
- project open $env(ISE_FILE)
- } else {
- puts ">>> Creating project: $env..."
- (file "C:/USRP2_fpga_NEMO/usrp2/top/tcl/ise_helper.tcl" line 41)
- make: *** [C:/USRP2_fpga_NEMO/usrp2/top/USRP2/build/u2_rev3.xise] Error 1
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