LIBRARY IEEE;
LIBRARY WORK;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY mux4to1 IS
	Port( w	: IN	STD_LOGIC_VECTOR(0 TO 3);
	      s	: IN	STD_LOGIC_VECTOR(1 DOWNTO 0);
	      f	: OUT	STD_LOGIC);
END mux4to1;


ARCHITECTURE Behavior OF mux4to1 IS

COMPONENT mux2to1 IS
	Port( w1: IN	STD_LOGIC;
	      w2: IN	STD_LOGIC;
	      s	: IN	STD_LOGIC;
	      f	: OUT	STD_LOGIC);
END COMPONENT;

SIGNAL f1, f2	: STD_LOGIC;

BEGIN
	Mux1: mux2to1 PORT MAP
		(w(0), w(1), s(0), f1);
	Mux2: mux2to1 PORT MAP
		(w(2), w(3), s(0), f2);
	Mux3: mux2to1 PORT MAP
		(f1, f2, s(1), f);
END Behavior;