/* Machine-generated using Migen */
module soc(
	output videoin_rst_n,
	input trigger_reset,
	output reg [23:0] adr,
	input clkin,
	output reg tx,
	input [15:0] d,
	output flash_rst_n,
	output oe_n,
	output we_n,
	output ce_n,
	output ac97_rst_n,
	input rx
);

reg wishbone_norflash_err_o;
wire csr_we_i;
reg [13:0] csr_from_wishbone_a_o;
wire [1:0] wishbone_lm32d_bte_o;
reg [3:0] tx_count16;
wire [2:0] wishbone_norflash_cti_i;
wire wishbone_to_csr_cyc_i;
wire lm32_I_RTY_I;
wire [13:0] csr_a_i;
reg [15:0] enable16_counter;
wire stat_thre_we;
wire [3:0] wishbone_norflash_sel_i;
wire [1:0] request;
wire [2:0] wishbone_to_csr_cti_i;
wire [29:0] wishbone_norflash_adr_i;
reg [1:0] wb2csr0_counter;
reg [4:0] norflash0_counter;
reg stat_thre;
reg wishbone_norflash_ack_o;
wire [31:0] wishbone_lm32i_dat_i;
reg [2:0] wishbone_shr_cti_o;
reg [7:0] csr_d_o;
wire [1:0] wishbone_norflash_bte_i;
wire [29:0] wishbone_to_csr_adr_i;
wire DCM_SP_RST;
reg tx_busy;
wire [3:0] wishbone_lm32d_sel_o;
wire wishbone_to_csr_stb_i;
wire wishbone_lm32i_cyc_o;
wire [31:0] lm32_D_ADR_O;
wire [31:0] wishbone_shr_dat_i;
wire wishbone_lm32d_stb_o;
wire wishbone_lm32i_err_i;
wire wishbone_lm32i_ack_i;
wire uart0_sel;
wire wishbone_norflash_cyc_i;
reg wishbone_shr_cyc_o;
wire stat_thre_w;
reg [1:0] interconnectshared0_slave_sel_r;
wire [2:0] wishbone_lm32i_cti_o;
wire [1:0] wishbone_to_csr_bte_i;
wire wishbone_norflash_stb_i;
reg wishbone_shr_stb_o;
wire [31:0] wishbone_to_csr_dat_i;
wire wishbone_norflash_we_i;
wire wishbone_shr_ack_i;
reg [31:0] wishbone_shr_dat_o;
wire DCM_SP_PSEN;
reg wishbone_shr_we_o;
reg csr_from_wishbone_we_o;
wire [7:0] csr_d_i;
wire [29:0] wishbone_lm32i_adr_o;
reg [3:0] tx_bitcount;
wire [31:0] wishbone_lm32d_dat_o;
wire [31:0] lm32_I_ADR_O;
reg [1:0] wishbone_shr_bte_o;
wire [31:0] wishbone_norflash_dat_i;
wire rxtx_re;
wire wishbone_shr_err_i;
wire [29:0] wishbone_lm32d_adr_o;
wire [1:0] wishbone_lm32i_bte_o;
wire enable16;
wire lm32_D_RTY_I;
wire [7:0] csr_from_wishbone_d_i;
wire wishbone_lm32d_we_o;
reg [7:0] tx_reg;
reg wishbone_to_csr_err_o;
wire [7:0] divisor_divisor_r;
reg [7:0] divisor_divisor;
reg [31:0] wishbone_to_csr_dat_o;
wire wishbone_lm32d_err_i;
reg grant;
wire [31:0] wishbone_lm32i_dat_o;
wire [3:0] wishbone_to_csr_sel_i;
reg [3:0] wishbone_shr_sel_o;
wire [31:0] wishbone_lm32d_dat_i;
wire [3:0] wishbone_lm32i_sel_o;
reg wishbone_to_csr_ack_o;
wire wishbone_lm32d_cyc_o;
wire [7:0] rxtx_r;
reg [31:0] wishbone_norflash_dat_o;
wire wishbone_lm32i_stb_o;
reg [7:0] csr_from_wishbone_d_o;
reg [29:0] wishbone_shr_adr_o;
wire wishbone_to_csr_we_i;
reg [1:0] interconnectshared0_slave_sel;
wire wishbone_lm32d_ack_i;
reg [7:0] rxtx_w;
wire wishbone_lm32i_we_o;
wire [2:0] wishbone_lm32d_cti_o;

// synthesis translate off
reg dummy_s;
initial dummy_s <= 1'b0;
// synthesis translate on
assign lm32_I_RTY_I = 1'd0;
assign lm32_D_RTY_I = 1'd0;
assign wishbone_lm32i_adr_o = lm32_I_ADR_O[31:2];
assign wishbone_lm32d_adr_o = lm32_D_ADR_O[31:2];
assign csr_a_i = csr_from_wishbone_a_o;
assign csr_we_i = csr_from_wishbone_we_o;
assign csr_d_i = csr_from_wishbone_d_o;
assign csr_from_wishbone_d_i = csr_d_o;
assign oe_n = 1'd0;
assign we_n = 1'd1;
assign ce_n = 1'd0;
assign uart0_sel = (csr_a_i[13:9] == 5'd0);
assign rxtx_r = csr_d_i[7:0];
assign rxtx_re = ((uart0_sel & csr_we_i) & (csr_a_i[1:0] == 2'd0));
assign divisor_divisor_r = divisor_divisor;
assign enable16 = (enable16_counter == 16'd0);
assign stat_thre_we = 1'd1;
assign stat_thre_w = (~tx_busy);
assign DCM_SP_PSEN = 1'd0;
assign DCM_SP_RST = 1'd0;

// synthesis translate off
reg dummy_d;
// synthesis translate on
always @(*) begin
	wishbone_shr_adr_o <= 30'd0;
	case (grant)
		1'd0: begin
			wishbone_shr_adr_o <= wishbone_lm32i_adr_o;
		end
		default: begin
			wishbone_shr_adr_o <= wishbone_lm32d_adr_o;
		end
	endcase
// synthesis translate off
	dummy_d <= dummy_s;
// synthesis translate on
end

// synthesis translate off
reg dummy_d_1;
// synthesis translate on
always @(*) begin
	wishbone_shr_dat_o <= 32'd0;
	case (grant)
		1'd0: begin
			wishbone_shr_dat_o <= wishbone_lm32i_dat_o;
		end
		default: begin
			wishbone_shr_dat_o <= wishbone_lm32d_dat_o;
		end
	endcase
// synthesis translate off
	dummy_d_1 <= dummy_s;
// synthesis translate on
end

// synthesis translate off
reg dummy_d_2;
// synthesis translate on
always @(*) begin
	wishbone_shr_sel_o <= 4'd0;
	case (grant)
		1'd0: begin
			wishbone_shr_sel_o <= wishbone_lm32i_sel_o;
		end
		default: begin
			wishbone_shr_sel_o <= wishbone_lm32d_sel_o;
		end
	endcase
// synthesis translate off
	dummy_d_2 <= dummy_s;
// synthesis translate on
end

// synthesis translate off
reg dummy_d_3;
// synthesis translate on
always @(*) begin
	wishbone_shr_cyc_o <= 1'd0;
	case (grant)
		1'd0: begin
			wishbone_shr_cyc_o <= wishbone_lm32i_cyc_o;
		end
		default: begin
			wishbone_shr_cyc_o <= wishbone_lm32d_cyc_o;
		end
	endcase
// synthesis translate off
	dummy_d_3 <= dummy_s;
// synthesis translate on
end

// synthesis translate off
reg dummy_d_4;
// synthesis translate on
always @(*) begin
	wishbone_shr_stb_o <= 1'd0;
	case (grant)
		1'd0: begin
			wishbone_shr_stb_o <= wishbone_lm32i_stb_o;
		end
		default: begin
			wishbone_shr_stb_o <= wishbone_lm32d_stb_o;
		end
	endcase
// synthesis translate off
	dummy_d_4 <= dummy_s;
// synthesis translate on
end

// synthesis translate off
reg dummy_d_5;
// synthesis translate on
always @(*) begin
	wishbone_shr_we_o <= 1'd0;
	case (grant)
		1'd0: begin
			wishbone_shr_we_o <= wishbone_lm32i_we_o;
		end
		default: begin
			wishbone_shr_we_o <= wishbone_lm32d_we_o;
		end
	endcase
// synthesis translate off
	dummy_d_5 <= dummy_s;
// synthesis translate on
end

// synthesis translate off
reg dummy_d_6;
// synthesis translate on
always @(*) begin
	wishbone_shr_cti_o <= 3'd0;
	case (grant)
		1'd0: begin
			wishbone_shr_cti_o <= wishbone_lm32i_cti_o;
		end
		default: begin
			wishbone_shr_cti_o <= wishbone_lm32d_cti_o;
		end
	endcase
// synthesis translate off
	dummy_d_6 <= dummy_s;
// synthesis translate on
end

// synthesis translate off
reg dummy_d_7;
// synthesis translate on
always @(*) begin
	wishbone_shr_bte_o <= 2'd0;
	case (grant)
		1'd0: begin
			wishbone_shr_bte_o <= wishbone_lm32i_bte_o;
		end
		default: begin
			wishbone_shr_bte_o <= wishbone_lm32d_bte_o;
		end
	endcase
// synthesis translate off
	dummy_d_7 <= dummy_s;
// synthesis translate on
end
assign wishbone_lm32i_dat_i = wishbone_shr_dat_i;
assign wishbone_lm32d_dat_i = wishbone_shr_dat_i;
assign wishbone_lm32i_ack_i = (wishbone_shr_ack_i & (grant == 1'd0));
assign wishbone_lm32d_ack_i = (wishbone_shr_ack_i & (grant == 1'd1));
assign wishbone_lm32i_err_i = (wishbone_shr_err_i & (grant == 1'd0));
assign wishbone_lm32d_err_i = (wishbone_shr_err_i & (grant == 1'd1));
assign request = {wishbone_lm32d_cyc_o, wishbone_lm32i_cyc_o};

// synthesis translate off
reg dummy_d_8;
// synthesis translate on
always @(*) begin
	interconnectshared0_slave_sel <= 2'd0;
	interconnectshared0_slave_sel[0] <= (wishbone_shr_adr_o[28:27] == 2'd0);
	interconnectshared0_slave_sel[1] <= (wishbone_shr_adr_o[28:27] == 2'd3);
// synthesis translate off
	dummy_d_8 <= dummy_s;
// synthesis translate on
end
assign wishbone_norflash_adr_i = wishbone_shr_adr_o;
assign wishbone_to_csr_adr_i = wishbone_shr_adr_o;
assign wishbone_norflash_dat_i = wishbone_shr_dat_o;
assign wishbone_to_csr_dat_i = wishbone_shr_dat_o;
assign wishbone_norflash_sel_i = wishbone_shr_sel_o;
assign wishbone_to_csr_sel_i = wishbone_shr_sel_o;
assign wishbone_norflash_stb_i = wishbone_shr_stb_o;
assign wishbone_to_csr_stb_i = wishbone_shr_stb_o;
assign wishbone_norflash_we_i = wishbone_shr_we_o;
assign wishbone_to_csr_we_i = wishbone_shr_we_o;
assign wishbone_norflash_cti_i = wishbone_shr_cti_o;
assign wishbone_to_csr_cti_i = wishbone_shr_cti_o;
assign wishbone_norflash_bte_i = wishbone_shr_bte_o;
assign wishbone_to_csr_bte_i = wishbone_shr_bte_o;
assign wishbone_norflash_cyc_i = (wishbone_shr_cyc_o & interconnectshared0_slave_sel[0]);
assign wishbone_to_csr_cyc_i = (wishbone_shr_cyc_o & interconnectshared0_slave_sel[1]);
assign wishbone_shr_ack_i = (wishbone_norflash_ack_o | wishbone_to_csr_ack_o);
assign wishbone_shr_err_i = (wishbone_norflash_err_o | wishbone_to_csr_err_o);
assign wishbone_shr_dat_i = (({32{interconnectshared0_slave_sel_r[0]}} & wishbone_norflash_dat_o) | ({32{interconnectshared0_slave_sel_r[1]}} & wishbone_to_csr_dat_o));

always @(posedge clkout) begin
	if (sys_rst) begin
		wishbone_to_csr_ack_o <= 1'd0;
		grant <= 1'd0;
		tx <= 1'd1;
		interconnectshared0_slave_sel_r <= 2'd0;
		csr_from_wishbone_we_o <= 1'd0;
		wishbone_norflash_dat_o <= 32'd0;
		tx_reg <= 8'd0;
		enable16_counter <= 16'd0;
		csr_from_wishbone_a_o <= 14'd0;
		wb2csr0_counter <= 2'd0;
		norflash0_counter <= 5'd0;
		wishbone_norflash_ack_o <= 1'd0;
		stat_thre <= 1'd0;
		tx_bitcount <= 4'd0;
		csr_from_wishbone_d_o <= 8'd0;
		tx_busy <= 1'd0;
		csr_d_o <= 8'd0;
		tx_count16 <= 4'd0;
		adr <= 24'd0;
		divisor_divisor <= 8'd0;
		wishbone_to_csr_dat_o <= 32'd0;
	end else begin
		csr_from_wishbone_we_o <= 1'd0;
		csr_from_wishbone_d_o <= wishbone_to_csr_dat_i;
		csr_from_wishbone_a_o <= wishbone_to_csr_adr_i[13:0];
		wishbone_to_csr_dat_o <= csr_from_wishbone_d_i;
		if ((wb2csr0_counter == 2'd1)) begin
			csr_from_wishbone_we_o <= wishbone_to_csr_we_i;
		end
		if ((wb2csr0_counter == 2'd2)) begin
			wishbone_to_csr_ack_o <= 1'd1;
		end
		if ((wb2csr0_counter == 2'd3)) begin
			wishbone_to_csr_ack_o <= 1'd0;
		end
		if ((wb2csr0_counter != 2'd0)) begin
			wb2csr0_counter <= (wb2csr0_counter + 2'd1);
		end else begin
			if ((wishbone_to_csr_cyc_i & wishbone_to_csr_stb_i)) begin
				wb2csr0_counter <= 2'd1;
			end
		end
		if (((wishbone_norflash_cyc_i & wishbone_norflash_stb_i) & (norflash0_counter == 5'd0))) begin
			adr <= {wishbone_norflash_adr_i[22:0], 1'd0};
		end
		if ((norflash0_counter == 5'd12)) begin
			wishbone_norflash_dat_o[31:16] <= d;
			adr <= {wishbone_norflash_adr_i[22:0], 1'd1};
		end
		if ((norflash0_counter == 5'd24)) begin
			wishbone_norflash_dat_o[15:0] <= d;
			wishbone_norflash_ack_o <= 1'd1;
		end
		if ((norflash0_counter == 5'd25)) begin
			wishbone_norflash_ack_o <= 1'd0;
		end
		if ((norflash0_counter == 5'd25)) begin
			norflash0_counter <= 5'd0;
		end else begin
			if ((norflash0_counter != 5'd0)) begin
				norflash0_counter <= (norflash0_counter + 5'd1);
			end else begin
				if ((wishbone_norflash_cyc_i & wishbone_norflash_stb_i)) begin
					norflash0_counter <= 5'd1;
				end
			end
		end
		if ((uart0_sel & csr_we_i)) begin
			case (csr_a_i[1:0])
				2'd1: begin
					divisor_divisor <= csr_d_i[0];
				end
			endcase
		end
		csr_d_o <= 8'd0;
		if (uart0_sel) begin
			case (csr_a_i[1:0])
				2'd0: begin
					csr_d_o <= rxtx_w;
				end
				2'd1: begin
					csr_d_o <= divisor_divisor;
				end
				2'd2: begin
					csr_d_o <= stat_thre;
				end
			endcase
		end
		if (stat_thre_we) begin
			stat_thre <= stat_thre_w;
		end
		enable16_counter <= (enable16_counter - 1'd1);
		if (enable16) begin
			enable16_counter <= 6'd42;
		end
		if (rxtx_re) begin
			tx_reg <= rxtx_r;
			tx_bitcount <= 1'd0;
			tx_count16 <= 1'd1;
			tx_busy <= 1'd1;
			tx <= 1'd0;
		end else begin
			if ((enable16 & tx_busy)) begin
				tx_count16 <= (tx_count16 + 1'd1);
				if ((tx_count16 == 4'd0)) begin
					tx_bitcount <= (tx_bitcount + 1'd1);
					if ((tx_bitcount == 4'd8)) begin
						tx <= 1'd1;
					end else begin
						if ((tx_bitcount == 4'd9)) begin
							tx <= 1'd1;
							tx_busy <= 1'd0;
						end else begin
							tx <= tx_reg[0];
							tx_reg <= {1'd0, tx_reg[7:1]};
						end
					end
				end
			end
		end
		case (grant)
			1'd0: begin
				if ((~request[0])) begin
					if (request[1]) begin
						grant <= 1'd1;
					end
				end
			end
			1'd1: begin
				if ((~request[1])) begin
					if (request[0]) begin
						grant <= 1'd0;
					end
				end
			end
		endcase
		interconnectshared0_slave_sel_r <= interconnectshared0_slave_sel;
	end
end

lm32_top lm32(
	.I_ERR_I(wishbone_lm32i_err_i),
	.I_DAT_I(wishbone_lm32i_dat_i),
	.D_RTY_I(lm32_D_RTY_I),
	.D_ACK_I(wishbone_lm32d_ack_i),
	.I_ACK_I(wishbone_lm32i_ack_i),
	.D_ERR_I(wishbone_lm32d_err_i),
	.interrupt(interrupt),
	.D_DAT_I(wishbone_lm32d_dat_i),
	.I_RTY_I(lm32_I_RTY_I),
	.I_WE_O(wishbone_lm32i_we_o),
	.I_ADR_O(lm32_I_ADR_O),
	.I_CTI_O(wishbone_lm32i_cti_o),
	.I_BTE_O(wishbone_lm32i_bte_o),
	.D_WE_O(wishbone_lm32d_we_o),
	.D_STB_O(wishbone_lm32d_stb_o),
	.D_BTE_O(wishbone_lm32d_bte_o),
	.I_CYC_O(wishbone_lm32i_cyc_o),
	.D_CYC_O(wishbone_lm32d_cyc_o),
	.D_SEL_O(wishbone_lm32d_sel_o),
	.I_SEL_O(wishbone_lm32i_sel_o),
	.I_LOCK_O(lm32_I_LOCK_O),
	.I_STB_O(wishbone_lm32i_stb_o),
	.I_DAT_O(wishbone_lm32i_dat_o),
	.D_CTI_O(wishbone_lm32d_cti_o),
	.D_DAT_O(wishbone_lm32d_dat_o),
	.D_LOCK_O(lm32_D_LOCK_O),
	.D_ADR_O(lm32_D_ADR_O),
	.clk_i(clkout),
	.rst_i(sys_rst)
);

DCM_SP #(
	.CLKDV_DIVIDE(2.0),
	.CLKFX_DIVIDE(5),
	.CLKFX_MULTIPLY(8),
	.CLKIN_DIVIDE_BY_2("FALSE"),
	.CLKIN_PERIOD(20.0),
	.CLKOUT_PHASE_SHIFT("NONE"),
	.CLK_FEEDBACK("NONE"),
	.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
	.DUTY_CYCLE_CORRECTION("TRUE"),
	.PHASE_SHIFT(0),
	.STARTUP_WAIT("TRUE")
) DCM_SP (
	.RST(DCM_SP_RST),
	.CLKIN(clkin),
	.PSEN(DCM_SP_PSEN),
	.CLKFX(clkout)
);

m1reset m1reset(
	.trigger_reset(trigger_reset),
	.flash_rst_n(flash_rst_n),
	.sys_rst(sys_rst),
	.videoin_rst_n(videoin_rst_n),
	.ac97_rst_n(ac97_rst_n),
	.sys_clk(clkout)
);

endmodule