// Old behaviour
/* Machine-generated using Migen */
module top(

);

reg [127:0] d;
wire [15:0] q;

// synthesis translate off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate on
assign q = d[64:1][32:1][16:1];

initial begin
	d <= 1'd0;
end

endmodule

// New behaviour
/* Machine-generated using Migen */
module top(

);

reg [127:0] d;
wire [15:0] q;

// synthesis translate off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate on
assign q = d[18:3];

initial begin
	d <= 1'd0;
end

endmodule