module keyboardInput_test( input ps2_clk, // PS/2 clock, ~12kHz input ps2_in, // PS/2 serial data input G_CLK, // global clock, 100kHz input reset, // reset used for clock debounce. output reg debounced_ps2_clk, // debounced PS/2 clock. output reg [0:6] sevenSeg // 7 segment display. ); /* * [0][LSB]xxxxxx[MSB][P][1] <-- Serial data as it is received. * * [1][P][MSB]xxxxxx[LSB][0] <-- Data after it is stored in the shift-right register. * * SCAN_DATA[8:1] signifies the 8-bit scan code for a key that is pressed. */ reg [10:0] SCAN_DATA; /* 8-bit scancode from keyboard in addition to the start, parity, and stop bit.*/ reg [10:0] temp_data; // temporary holder of incoming PS/2 data. reg [3:0] counter; // counts negative clock edges. reg busy; // indicates incoming data from the PS/2 module. /**--Clk debouncing declarations--**/ parameter NDELAY = 524287; parameter NBITS = 19; reg [NBITS-1:0] deb_count; reg xnew; /**-------------------------------**/ always @(posedge G_CLK) begin // debounce the PS/2 clock. if (reset) begin xnew <= ps2_clk; debounced_ps2_clk <= ps2_clk; deb_count <= 0; end else if (ps2_clk != xnew) begin xnew <= ps2_clk; deb_count <= 0; end else if (deb_count == NDELAY) debounced_ps2_clk <= xnew; else deb_count <= deb_count + 1; end // done with debounce. integer k; always @(negedge debounced_ps2_clk) begin for (k=0; k!=10; k=k+1) // shift-right register for incoming data. temp_data[k] <= temp_data[k+1]; temp_data[10] <= ps2_in; end always @(negedge debounced_ps2_clk) begin if (counter == 10) // counts 11 clock edges. counter <= 0; else counter <= counter + 1; end always @(posedge G_CLK) begin // busy goes LOW on the 11th clock edge. if (counter == 0 && (ps2_clk)) busy <= 0; else busy <= 1; end always@ (negedge busy) // data transfer is considered to be complete SCAN_DATA <= temp_data; // on the falling edge of the "busy" signal. always@ (SCAN_DATA) begin // display the numbers pressed on the keyboard. case(SCAN_DATA[8:1]) //7'bABCDEFG 8'h16: sevenSeg <= 7'b0110000; // '1' code 8'h1E: sevenSeg <= 7'b1101101; // '2' 8'h26: sevenSeg <= 7'b1111001; // '3' 8'h25: sevenSeg <= 7'b0110011; // '4' 8'h2E: sevenSeg <= 7'b1011011; // '5' 8'h36: sevenSeg <= 7'b1011111; // '6' 8'h3D: sevenSeg <= 7'b1110000; // '7' 8'h3E: sevenSeg <= 7'b1111111; // '8' 8'h46: sevenSeg <= 7'b1111011; // '9' 8'h45: sevenSeg <= 7'b1111110; // '0' 8'hF0: sevenSeg <= 7'bx; // "key released" code default: sevenSeg <= 7'bx; endcase end endmodule