from migen.fhdl.structure import *
from migen.fhdl.module import Module
from migen.fhdl import verilog

def foo1(x):
	return x[1:65]
	
def foo2(x):
	return x[1:33]
	
def foo3(x):
	return x[1:17]

class Example(Module):
	def __init__(self):
	
		d = Signal(128)
		q = Signal(16)
	
		self.comb += q.eq(foo3(foo2(foo1(d))))

print(verilog.convert(Example()))