/* $Log: flash_dev.h,v $ Revision 1.8 2008/01/18 08:53:26 Lingzhaojun no message Revision 1.7 2007/12/12 02:39:04 Fangzhenfu Îļþϵͳ¸üУ¡ FLASH µ×²ã¸üУ¡ Revision 1.6 2007/11/27 14:01:34 Huangshilin ÐÞ¸Ä ÒôƵˢÆÁÔëÒô,ϵͳ·´Ó¦ÂýµÄ BUG. Revision 1.5 2007/11/21 13:13:46 Fangzhenfu ɾ³ý¾ÉµÄÉý¼¶¹¤¾ß£¡Í³Ò»²ÉÓÃÐµĹ¤¾ß¸úÎļþϵͳ¡¢USB Revision 1.4 2007/11/07 07:25:50 Fangzhenfu USB ÌáËÙ£¨Ð¡ÎļþÌáËÙ£¬Ä¿Ç°ËÙ¶Èд 3M ×óÓÒ£¬¶Á 6.5M×óÓÒ£¬ 4K PAGE FLASH ¿Éµ½ 5M£¬8M£©£¬ ÎļþϵͳÐ޸ģ¡ ¼ÓÈë FLASH ·ÃÎÊʱÐò API £¡ ¼û flash_dev.h ÖÐ FlashTimingCfg£¨uint32 Freq£© Freq Ϊ×ÜÏßƵÂÊ---´ò°ü µÚÒ»´Îµ÷Óà FlashTimingCfg£¨£©Ê±ÇëÔÚ FS_Init() Ö®ºóµ÷Óã¬ÆäËüÔÚ×ÜÏßƵÂʱ仯ʱµ÷Óã¡ Revision 1.3 2007/10/08 02:58:36 Lingzhaojun Ìí¼Ó°æ±¾×Ô¶¯×¢Êͽű¾ */ #ifndef _FS_FLASH_DEV_H_ #define _FS_FLASH_DEV_H_ #include "stdio.h" #include "string.h" #undef EXT #ifdef _IN_FS_FLASH_DEV_ #define EXT #else #define EXT extern #endif /* ******************************************************************************* Flash Ïà¹ØµÄÅäÖÃÐÅÏ¢ ×¢£ºÊ¹Óà Lib Îļþʱ£¬ÏÂÃæµÄºê¶¨Òå²¢²»Æð×÷Óã¬Ö»Ìṩһ¸ö²Î¿¼µ±Ç°ËùÓõĿâµÄÅäÖà ******************************************************************************* */ #define DISK_SYS 0 //CÅÌ #define DISK_FLASH_1 1 #define DISK_FLASH_2 2 #define DISK_FLASH_3 3 #define DISK_FLASH_4 4 #define DISK_FLASH_5 5 #define DISK_FLASH_6 6 #define DISK_FLASH_7 7 #define DISK_FLASH_8 8 #define DISK_FLASH_9 9 #define DISK_FLASH_10 10 #define DISK_FLASH_11 11 #define DISK_FLASH_12 12 #define DISK_FLASH_13 13 #define DISK_FLASH_14 14 #define DISK_FLASH_15 15 #define DISK_FLASH_16 16 //1¿ÉÅäÖòÎÊý //#define BOOT_ONLY //¶¨ÒåÖ»Éú³ÉÖмä¼þÒýµ¼´úÂë, ²»¶¨ÒåÔòÊÇÍêÕûµÄÎļþϵͳ #ifndef BOOT_ONLY //#define DEBUG_FLASH //¶¨ÒåFLASHµ÷ÊÔģʽʹÄÜ //#define IN_SYSTEM //ǶÈ뵽ϵͳÈí¼þʱ¶¨Òå //#define OS_FILE //¶¨ÒåOSϵÄÎļþϵͳ #endif #ifndef SETUP #define USB //¶¨ÒåʹÄÜUSB #endif #define DUAL_PLANE //¶¨ÒåNAND FLASH DUAL PLANE²ÁдʹÄÜ #define SYS_PROTECT //¶¨Òåϵͳ±£ÁôÇøдʹÄÜ //#define VIRTUAL_MEMORY 0x400000 //¶¨ÒåÐéÄâÄÚ´æ2GB #define SYS_DISK_HID 0 //ϵͳÅÌʹÄÜ, 1=Òþ²Ø, 0=ÏÔʾ #if(RK27XX_IO_MEMMAP == LDK_MMU_DISABLE) #define RegNandCtrlBase 0x1E740000 //from mail.h #define INTC0_VIR_ARRD 0x19C40000 #define UDC_BASE 0x19CC0000 #define ARM7_CACHE_CON_BASE 0xEFFF0000 #define HDMA_BASE 0x1E700000 #define SRAM_BASE_ADDR 0x18200000 //SRAMµÄ×îºó512B #define SDRAM_BASE_ADDR 0x17000000 #elif(RK27XX_IO_MEMMAP == LDK_MMU_ENABLE) #define RegNandCtrlBase 0x02440000 //from mail.h #define INTC0_VIR_ARRD 0x02040000 #define UDC_BASE 0x020C0000 #define ARM7_CACHE_CON_BASE 0xEFFF0000 #define HDMA_BASE 0x02400000 #define SRAM_BASE_ADDR 0x18200000 //SRAMµÄ×îºó512B #define SDRAM_BASE_ADDR 0x01000000 #elif(RK27XX_IO_MEMMAP == PORSCHE9_IO_MEMMAP) #define RegNandCtrlBase 0x180E8000 //from mail.h #define INTC0_VIR_ARRD 0x18080000 #define UDC_BASE 0x180A0000 #define ARM7_CACHE_CON_BASE 0xEFFF0000 #define HDMA_BASE 0x18090000 #define SRAM_BASE_ADDR 0x18200000 //SRAMµÄ×îºó512B #define SDRAM_BASE_ADDR 0x60000000 #else #undef RegNandCtrlBase #undef INTC0_VIR_ARRD #undef UDC_BASE #undef ARM7_CACHE_CON_BASE #undef HDMA_BASE #undef SRAM_BASE_ADDR #undef SDRAM_BASE_ADDR #endif #define FLASH0_DATA (RegNandCtrlBase+0x0200) #define FLASH0_ADDR (RegNandCtrlBase+0x0204) #define FLASH0_CMD (RegNandCtrlBase+0x0208) #define FLASH0_0 (RegNandCtrlBase+0x0a00) #define SPARE0_0 (RegNandCtrlBase+0x1200) #endif