LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY test9 IS
END test9;
 
ARCHITECTURE behavior OF test9 IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT partial
    PORT(
         A : IN  bit_vector(17 downto 0);
         B : IN  bit_vector(17 downto 0);
         C : OUT  bit_vector(35 downto 0);
         D : OUT  bit
        );
    END COMPONENT;
    

   --Inputs
   signal A : bit_vector(17 downto 0) := (others => '0');
   signal B : bit_vector(17 downto 0) := (others => '0');

 	--Outputs
   signal C : bit_vector(35 downto 0);
   signal D : bit;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
   --constant <clock>_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: partial PORT MAP (
          A => A,
          B => B,
          C => C,
          D => D
        );

 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		A<="111111111111111111";
		B<="111111111111111111";
      --wait for <clock>_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;