/* wait for reset */ while((AT91C_BASE_RSTC->RSTC_RSR & (AT91C_RSTC_SRCMP | AT91C_RSTC_NRSTL)) != AT91C_RSTC_NRSTL) ; /* enable reset */ AT91C_BASE_RSTC->RSTC_RMR = ((0xA5 << 24) | AT91C_RSTC_URSTEN); /* Flash Memory: 1 wait state, about 50 cycles in a microsecond.*/ AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; /* Enables the main oscillator and waits 56 slow cycles as startup time.*/ AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)) ; /* PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10 PLLfreq = 96109714 Hz (rounded).*/ AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) | (AT91C_CKGR_PLLCOUNT & (10 << 8)) | (AT91C_CKGR_USBDIV_1) | (AT91C_CKGR_MUL & (72 << 16)); while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) ; /* Master clock = PLLfreq / 2 = 48054858 Hz (rounded).*/ AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2; while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) ;