*(int*)(spi_base+ECSPI2_CONREG) = 0x00 ; // enable bit OFF, to reset block
	*(int*)(spi_base+ECSPI2_CONREG) |= (1<<4) | (1<<3) ; // channel 0 - master
	// CONREG: 19-18 : 00=channel 0 select (SS0), 
	//         7-4 : CHANNEL MODE 0-slave/1-master, [3]-channel 3... [0]-channel 0 
	//         3: SMC - immediately starts SPI burst when data is written to TXFIFO
	
	printf ("========= Configure SPI =============\n") ;
	*(int*)(spi_base+ECSPI2_CONREG) |= 0x01; // enable bit ON
	*(int*)(spi_base+ECSPI2_DMAREG) = 0; // = (1<<23); 
	// DMAREG: 
	//   23-RXDEN-RXFIFO DMA request enable
	*(int*)(spi_base+ECSPI2_PERIODREG) = (1<<15) ; 
// PERIODREG: 
//    15 - CSRC : 0-Spi clock, 1- Low freq ref clk 32.768Khz	
	*(int*)(spi_base+ECSPI2_TESTREG) = (1<<31) ; 
	// TESTREG: 
	//   31- LBC: 1- loopback enabled - receiver is connected to transmitter