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By: a guest on Jun 2nd, 2012  |  syntax: None  |  size: 1.51 KB  |  hits: 12  |  expires: Never
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  1. .include "m64def.inc"
  2.  
  3. .def secunde  = r22
  4. .def minute = r23
  5. .def ore = r24
  6.  
  7. main:
  8.   ldi secunde, 0x0
  9.   ldi minute, 0x0
  10.   ldi ore, 0x0
  11.  
  12.        
  13.  
  14.         ldi r16, (1<<CS02)|(1<<CS01)|(1<<CS00)
  15.         out TCCR0,r16 ; Timer clock = system clock / 1024
  16.         ldi r16,1<<TOV0
  17.         out TIFR,r16 ; Clear TOV0/ clear pending interrupts
  18.         ldi r16,1<<TOIE0
  19.         out TIMSK,r16 ; Enable Timer/Counter0 Overflow Interrupt
  20.         ser r16
  21.         out DDRE,r16 ; Set Port E as output
  22.  
  23.         sei
  24.  
  25.         ldi r16, low(RAMEND)
  26.         out SPL, r16
  27.         ldi r16, high(RAMEND)
  28.         out SPH, r16
  29.  
  30.         ldi r16, 0b00011000 ; activare Rx si Tx
  31.         sts UCSR1B,r16
  32.         ldi r16, 0b00001110 ; dimensiune frame 8 biti, fara paritate, 2 biti de stop
  33.         sts UCSR1C,r16
  34.         ldi r16, 0x30 ; Baud rate calculat, incape in primii 8 biti
  35.         ldi r17, 0 ; Bitii superiori la UBRR sunt zero
  36.         sts UBRR1H, r17
  37.         sts UBRR1L, r16
  38.  
  39.  
  40.  
  41.  
  42.  
  43.  
  44.  
  45.  
  46.  
  47.  
  48.  
  49. ;ISR_TOV0:
  50. timer0_overflow:
  51.         push r15
  52.         in r15,SREG
  53.         push r15
  54.  
  55.         inc r18
  56.         cpi r18, $99
  57.         breq step
  58.         rjmp retia
  59.  
  60.  
  61.  
  62. resetsec:
  63.   ldi secunde, 0
  64.   inc minute
  65.   rjmp step
  66.  
  67. resetmin:
  68.   ldi minute, 0
  69.   inc ore
  70.   rjmp step
  71.  
  72. resetore:
  73.   ldi ore, 0
  74.   rjmp step
  75.  
  76. step:
  77.  
  78.  
  79. CPI secunde, 0x02 ;aici tre sa fie 3B
  80.   BREQ resetsec
  81.  
  82.   CPI minute, 0x02 ;si aici
  83.   BREQ resetmin
  84.  
  85.   CPI ore, 0x02 ;aici 17
  86.   BREQ resetore
  87.  
  88.   inc secunde
  89.   clr r18
  90.  
  91.   ldi r16,0x3A
  92.         sts UDR1,r16 ; scriere date spre transmisie
  93.         txloop3:
  94.                         lds r20, UCSR1A ; asteptare terminare transmisie
  95.                         sbrs r20, 5
  96.                         rjmp txloop3
  97.  
  98.  
  99. retia:
  100.         pop r15
  101.         out SREG,r15
  102.         pop r15
  103.  
  104. reti
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