module clock_divider(
    input clk_50MHz,
    output reg clk_1Hz
    );

	reg [25:0] count;
	initial count = 0;
	initial clk_1Hz = 0;
	always @(posedge clk_50MHz)
	begin
		if(count < 25'd25000000)
			count=count+1;
		else
		begin
			count = 25'd0;
			clk_1Hz = !clk_1Hz;
		end
	end
endmodule