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rt5350 wlan support for compat-wireless-2012-09-07

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  1. --- a/rt2x00.h 2012-12-19 19:25:11.000000000 +0600
  2. +++ b/rt2x00.h 2012-12-02 17:08:15.000000000 +0600
  3. @@ -194,6 +194,7 @@
  4. #define RT3572 0x3572
  5. #define RT3593 0x3593
  6. #define RT3883 0x3883 /* WSOC */
  7. +#define RT5350 0x5350 /* WSOC 2.4GHz */
  8. #define RT5390 0x5390 /* 2.4GHz */
  9. #define RT5392 0x5392 /* 2.4GHz */
  10.  
  11. --- a/rt2800.h 2012-12-19 19:25:10.000000000 +0600
  12. +++ b/rt2800.h 2012-12-02 16:59:36.000000000 +0600
  13. @@ -69,6 +69,7 @@
  14. #define RF3322 0x000c
  15. #define RF3053 0x000d
  16. #define RF3290 0x3290
  17. +#define RF5350 0x5350
  18. #define RF5360 0x5360
  19. #define RF5370 0x5370
  20. #define RF5372 0x5372
  21. --- a/rt2800lib.c 2012-12-19 19:25:11.000000000 +0600
  22. +++ b/rt2800lib.c 2012-12-18 20:37:18.000000000 +0600
  23. @@ -2159,6 +2159,15 @@
  24. if (rf->channel <= 14) {
  25. int idx = rf->channel-1;
  26.  
  27. + if (rt2x00_rt(rt2x00dev, RT5350)) {
  28. + static const char r59_non_bt[] = {0x0b, 0x0b,
  29. + 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
  30. + 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
  31. +
  32. + rt2800_rfcsr_write(rt2x00dev, 59,
  33. + r59_non_bt[idx]);
  34. + }
  35. +
  36. if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
  37. if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
  38. /* r55/r59 value array of channel 1~14 */
  39. @@ -2204,6 +2213,7 @@
  40. }
  41. }
  42. }
  43. +
  44. }
  45.  
  46. static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
  47. @@ -2240,6 +2250,7 @@
  48. case RF3322:
  49. rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
  50. break;
  51. + case RF5350:
  52. case RF5360:
  53. case RF5370:
  54. case RF5372:
  55. @@ -2253,6 +2264,7 @@
  56.  
  57. if (rt2x00_rf(rt2x00dev, RF3290) ||
  58. rt2x00_rf(rt2x00dev, RF3322) ||
  59. + rt2x00_rf(rt2x00dev, RF5350) ||
  60. rt2x00_rf(rt2x00dev, RF5360) ||
  61. rt2x00_rf(rt2x00dev, RF5370) ||
  62. rt2x00_rf(rt2x00dev, RF5372) ||
  63. @@ -2383,7 +2395,8 @@
  64. /*
  65. * Clear update flag
  66. */
  67. - if (rt2x00_rt(rt2x00dev, RT3352)) {
  68. + if (rt2x00_rt(rt2x00dev, RT3352) ||
  69. + rt2x00_rt(rt2x00dev, RT5350)) {
  70. rt2800_bbp_read(rt2x00dev, 49, &bbp);
  71. rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
  72. rt2800_bbp_write(rt2x00dev, 49, bbp);
  73. @@ -2768,6 +2781,7 @@
  74. rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
  75. break;
  76. case RF3290:
  77. + case RF5350:
  78. case RF5360:
  79. case RF5370:
  80. case RF5372:
  81. @@ -3083,8 +3097,9 @@
  82. } else if (rt2x00_rt(rt2x00dev, RT3572)) {
  83. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
  84. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  85. - } else if (rt2x00_rt(rt2x00dev, RT5390) ||
  86. - rt2x00_rt(rt2x00dev, RT5392)) {
  87. + } else if (rt2x00_rt(rt2x00dev, RT5350) ||
  88. + rt2x00_rt(rt2x00dev, RT5390) ||
  89. + rt2x00_rt(rt2x00dev, RT5392)) {
  90. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
  91. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  92. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  93. @@ -3465,6 +3480,10 @@
  94. rt2800_bbp_write(rt2x00dev, 4, 0x50);
  95. }
  96.  
  97. + if (rt2x00_rt(rt2x00dev, RT5350)) {
  98. + rt2800_bbp_write(rt2x00dev, 4, 0x50);
  99. + }
  100. +
  101. if (rt2x00_rt(rt2x00dev, RT3290) ||
  102. rt2x00_rt(rt2x00dev, RT5390) ||
  103. rt2x00_rt(rt2x00dev, RT5392)) {
  104. @@ -3477,11 +3496,13 @@
  105. rt2x00_rt(rt2x00dev, RT3290) ||
  106. rt2x00_rt(rt2x00dev, RT3352) ||
  107. rt2x00_rt(rt2x00dev, RT3572) ||
  108. + rt2x00_rt(rt2x00dev, RT5350) ||
  109. rt2x00_rt(rt2x00dev, RT5390) ||
  110. rt2x00_rt(rt2x00dev, RT5392))
  111. rt2800_bbp_write(rt2x00dev, 31, 0x08);
  112.  
  113. - if (rt2x00_rt(rt2x00dev, RT3352))
  114. + if (rt2x00_rt(rt2x00dev, RT3352) ||
  115. + rt2x00_rt(rt2x00dev, RT5350))
  116. rt2800_bbp_write(rt2x00dev, 47, 0x48);
  117.  
  118. rt2800_bbp_write(rt2x00dev, 65, 0x2c);
  119. @@ -3489,6 +3510,7 @@
  120.  
  121. if (rt2x00_rt(rt2x00dev, RT3290) ||
  122. rt2x00_rt(rt2x00dev, RT3352) ||
  123. + rt2x00_rt(rt2x00dev, RT5350) ||
  124. rt2x00_rt(rt2x00dev, RT5390) ||
  125. rt2x00_rt(rt2x00dev, RT5392))
  126. rt2800_bbp_write(rt2x00dev, 68, 0x0b);
  127. @@ -3498,6 +3520,7 @@
  128. rt2800_bbp_write(rt2x00dev, 73, 0x12);
  129. } else if (rt2x00_rt(rt2x00dev, RT3290) ||
  130. rt2x00_rt(rt2x00dev, RT3352) ||
  131. + rt2x00_rt(rt2x00dev, RT5350) ||
  132. rt2x00_rt(rt2x00dev, RT5390) ||
  133. rt2x00_rt(rt2x00dev, RT5392)) {
  134. rt2800_bbp_write(rt2x00dev, 69, 0x12);
  135. @@ -3529,7 +3552,8 @@
  136. } else if (rt2800_is_305x_soc(rt2x00dev)) {
  137. rt2800_bbp_write(rt2x00dev, 78, 0x0e);
  138. rt2800_bbp_write(rt2x00dev, 80, 0x08);
  139. - } else if (rt2x00_rt(rt2x00dev, RT3352)) {
  140. + } else if (rt2x00_rt(rt2x00dev, RT3352) ||
  141. + rt2x00_rt(rt2x00dev, RT5350)) {
  142. rt2800_bbp_write(rt2x00dev, 78, 0x0e);
  143. rt2800_bbp_write(rt2x00dev, 80, 0x08);
  144. rt2800_bbp_write(rt2x00dev, 81, 0x37);
  145. @@ -3546,6 +3570,7 @@
  146.  
  147. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  148. if (rt2x00_rt(rt2x00dev, RT3290) ||
  149. + rt2x00_rt(rt2x00dev, RT5350) ||
  150. rt2x00_rt(rt2x00dev, RT5390) ||
  151. rt2x00_rt(rt2x00dev, RT5392))
  152. rt2800_bbp_write(rt2x00dev, 83, 0x7a);
  153. @@ -3555,6 +3580,7 @@
  154. if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
  155. rt2800_bbp_write(rt2x00dev, 84, 0x19);
  156. else if (rt2x00_rt(rt2x00dev, RT3290) ||
  157. + rt2x00_rt(rt2x00dev, RT5350) ||
  158. rt2x00_rt(rt2x00dev, RT5390) ||
  159. rt2x00_rt(rt2x00dev, RT5392))
  160. rt2800_bbp_write(rt2x00dev, 84, 0x9a);
  161. @@ -3563,6 +3589,7 @@
  162.  
  163. if (rt2x00_rt(rt2x00dev, RT3290) ||
  164. rt2x00_rt(rt2x00dev, RT3352) ||
  165. + rt2x00_rt(rt2x00dev, RT5350) ||
  166. rt2x00_rt(rt2x00dev, RT5390) ||
  167. rt2x00_rt(rt2x00dev, RT5392))
  168. rt2800_bbp_write(rt2x00dev, 86, 0x38);
  169. @@ -3577,6 +3604,7 @@
  170.  
  171. if (rt2x00_rt(rt2x00dev, RT3290) ||
  172. rt2x00_rt(rt2x00dev, RT3352) ||
  173. + rt2x00_rt(rt2x00dev, RT5350) ||
  174. rt2x00_rt(rt2x00dev, RT5390) ||
  175. rt2x00_rt(rt2x00dev, RT5392))
  176. rt2800_bbp_write(rt2x00dev, 92, 0x02);
  177. @@ -3595,6 +3623,7 @@
  178. rt2x00_rt(rt2x00dev, RT3290) ||
  179. rt2x00_rt(rt2x00dev, RT3352) ||
  180. rt2x00_rt(rt2x00dev, RT3572) ||
  181. + rt2x00_rt(rt2x00dev, RT5350) ||
  182. rt2x00_rt(rt2x00dev, RT5390) ||
  183. rt2x00_rt(rt2x00dev, RT5392) ||
  184. rt2800_is_305x_soc(rt2x00dev))
  185. @@ -3604,6 +3633,7 @@
  186.  
  187. if (rt2x00_rt(rt2x00dev, RT3290) ||
  188. rt2x00_rt(rt2x00dev, RT3352) ||
  189. + rt2x00_rt(rt2x00dev, RT5350) ||
  190. rt2x00_rt(rt2x00dev, RT5390) ||
  191. rt2x00_rt(rt2x00dev, RT5392))
  192. rt2800_bbp_write(rt2x00dev, 104, 0x92);
  193. @@ -3614,13 +3644,15 @@
  194. rt2800_bbp_write(rt2x00dev, 105, 0x1c);
  195. else if (rt2x00_rt(rt2x00dev, RT3352))
  196. rt2800_bbp_write(rt2x00dev, 105, 0x34);
  197. - else if (rt2x00_rt(rt2x00dev, RT5390) ||
  198. + else if (rt2x00_rt(rt2x00dev, RT5350) ||
  199. + rt2x00_rt(rt2x00dev, RT5390) ||
  200. rt2x00_rt(rt2x00dev, RT5392))
  201. rt2800_bbp_write(rt2x00dev, 105, 0x3c);
  202. else
  203. rt2800_bbp_write(rt2x00dev, 105, 0x05);
  204.  
  205. if (rt2x00_rt(rt2x00dev, RT3290) ||
  206. + rt2x00_rt(rt2x00dev, RT5350) ||
  207. rt2x00_rt(rt2x00dev, RT5390))
  208. rt2800_bbp_write(rt2x00dev, 106, 0x03);
  209. else if (rt2x00_rt(rt2x00dev, RT3352))
  210. @@ -3630,10 +3662,12 @@
  211. else
  212. rt2800_bbp_write(rt2x00dev, 106, 0x35);
  213.  
  214. - if (rt2x00_rt(rt2x00dev, RT3352))
  215. + if (rt2x00_rt(rt2x00dev, RT3352) ||
  216. + rt2x00_rt(rt2x00dev, RT5350))
  217. rt2800_bbp_write(rt2x00dev, 120, 0x50);
  218.  
  219. if (rt2x00_rt(rt2x00dev, RT3290) ||
  220. + rt2x00_rt(rt2x00dev, RT5350) ||
  221. rt2x00_rt(rt2x00dev, RT5390) ||
  222. rt2x00_rt(rt2x00dev, RT5392))
  223. rt2800_bbp_write(rt2x00dev, 128, 0x12);
  224. @@ -3643,13 +3677,15 @@
  225. rt2800_bbp_write(rt2x00dev, 135, 0xf6);
  226. }
  227.  
  228. - if (rt2x00_rt(rt2x00dev, RT3352))
  229. + if (rt2x00_rt(rt2x00dev, RT3352) ||
  230. + rt2x00_rt(rt2x00dev, RT5350))
  231. rt2800_bbp_write(rt2x00dev, 137, 0x0f);
  232.  
  233. if (rt2x00_rt(rt2x00dev, RT3071) ||
  234. rt2x00_rt(rt2x00dev, RT3090) ||
  235. rt2x00_rt(rt2x00dev, RT3390) ||
  236. rt2x00_rt(rt2x00dev, RT3572) ||
  237. + rt2x00_rt(rt2x00dev, RT5350) ||
  238. rt2x00_rt(rt2x00dev, RT5390) ||
  239. rt2x00_rt(rt2x00dev, RT5392)) {
  240. rt2800_bbp_read(rt2x00dev, 138, &value);
  241. @@ -3686,7 +3722,8 @@
  242. rt2800_bbp_write(rt2x00dev, 3, value);
  243. }
  244.  
  245. - if (rt2x00_rt(rt2x00dev, RT3352)) {
  246. + if (rt2x00_rt(rt2x00dev, RT3352) ||
  247. + rt2x00_rt(rt2x00dev, RT5350)) {
  248. rt2800_bbp_write(rt2x00dev, 163, 0xbd);
  249. /* Set ITxBF timeout to 0x9c40=1000msec */
  250. rt2800_bbp_write(rt2x00dev, 179, 0x02);
  251. @@ -3708,6 +3745,14 @@
  252. rt2800_bbp_write(rt2x00dev, 148, 0xc8);
  253. }
  254.  
  255. + if (rt2x00_rt(rt2x00dev, RT5350)) {
  256. + rt2800_bbp_write(rt2x00dev, 150, 0x40); /* Antenna Software OFDM */
  257. + rt2800_bbp_write(rt2x00dev, 151, 0x30); /* Antenna Software CCK */
  258. + rt2800_bbp_write(rt2x00dev, 152, 0xa3);
  259. + rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
  260. + }
  261. +
  262. +
  263. if (rt2x00_rt(rt2x00dev, RT5390) ||
  264. rt2x00_rt(rt2x00dev, RT5392)) {
  265. int ant, div_mode;
  266. @@ -3844,6 +3889,7 @@
  267. !rt2x00_rt(rt2x00dev, RT3352) &&
  268. !rt2x00_rt(rt2x00dev, RT3390) &&
  269. !rt2x00_rt(rt2x00dev, RT3572) &&
  270. + !rt2x00_rt(rt2x00dev, RT5350) &&
  271. !rt2x00_rt(rt2x00dev, RT5390) &&
  272. !rt2x00_rt(rt2x00dev, RT5392) &&
  273. !rt2800_is_305x_soc(rt2x00dev))
  274. @@ -3854,6 +3900,7 @@
  275. */
  276. if (rt2x00_rt(rt2x00dev, RT3290) ||
  277. rt2x00_rt(rt2x00dev, RT3352) ||
  278. + rt2x00_rt(rt2x00dev, RT5350) ||
  279. rt2x00_rt(rt2x00dev, RT5390) ||
  280. rt2x00_rt(rt2x00dev, RT5392)) {
  281. rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
  282. @@ -4127,6 +4174,75 @@
  283. rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
  284. rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
  285. rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
  286. + } else if (rt2x00_rt(rt2x00dev, RT5350)) {
  287. + struct rt2x00_platform_data *pdata = rt2x00dev->dev->platform_data;
  288. +
  289. + rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
  290. + rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
  291. + rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
  292. + rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
  293. + rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
  294. + rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
  295. + rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
  296. + rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
  297. + rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
  298. + rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
  299. + rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
  300. + rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
  301. + rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
  302. + if(pdata && pdata->clk_is_20mhz)
  303. + rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);/*if clk_is_20mhz - 0x1f else 0x9f*/
  304. + else
  305. + rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
  306. + rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
  307. + rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
  308. + rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
  309. + rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
  310. + rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
  311. + rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
  312. + rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
  313. + rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
  314. + rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
  315. + rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
  316. + rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
  317. + rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
  318. + rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
  319. + rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
  320. + rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
  321. + rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
  322. + rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
  323. + rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
  324. + rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
  325. + rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
  326. + rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
  327. + rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
  328. + rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
  329. + rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
  330. + rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
  331. + rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
  332. + rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
  333. + rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
  334. + rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
  335. + rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
  336. + rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
  337. + rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
  338. + rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
  339. + rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
  340. + rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
  341. + rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
  342. + rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
  343. + rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
  344. + rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
  345. + rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
  346. + rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
  347. + rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
  348. + rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
  349. + rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
  350. + rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
  351. + rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
  352. + rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
  353. + rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
  354. + rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
  355. } else if (rt2x00_rt(rt2x00dev, RT5390)) {
  356. rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
  357. rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
  358. @@ -4653,6 +4769,12 @@
  359. if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
  360. rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
  361. rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
  362. + } else if(rt2x00_rt(rt2x00dev, RT5350)) {
  363. + rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 1);
  364. + rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
  365. + rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF3320);
  366. + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
  367. + EEPROM(rt2x00dev, "rt5350: Ant: 0x%04x\n", word);
  368. }
  369.  
  370. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
  371. @@ -4777,6 +4899,8 @@
  372. rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
  373. rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
  374. rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
  375. + else if(rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5350)
  376. + value = RF5350;
  377. else
  378. value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
  379.  
  380. @@ -4794,6 +4918,7 @@
  381. case RT3352:
  382. case RT3390:
  383. case RT3572:
  384. + case RT5350:
  385. case RT5390:
  386. case RT5392:
  387. break;
  388. @@ -4815,6 +4940,7 @@
  389. case RF3290:
  390. case RF3320:
  391. case RF3322:
  392. + case RF5350:
  393. case RF5360:
  394. case RF5370:
  395. case RF5372:
  396. @@ -5177,7 +5303,8 @@
  397. rt2x00_rf(rt2x00dev, RF5392)) {
  398. spec->num_channels = 14;
  399. spec->channels = rf_vals_3x;
  400. - } else if (rt2x00_rf(rt2x00dev, RF3322)) {
  401. + } else if (rt2x00_rf(rt2x00dev, RF3322) ||
  402. + rt2x00_rf(rt2x00dev, RF5350)) {
  403. spec->num_channels = 14;
  404. if (spec->clk_is_20mhz)
  405. spec->channels = rf_vals_xtal20mhz_3x;
  406. @@ -5266,6 +5393,7 @@
  407. case RF3290:
  408. case RF5360:
  409. case RF5370:
  410. + case RF5350:
  411. case RF5372:
  412. case RF5390:
  413. case RF5392:
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