/* processor status */
enum {
PSW_IE = (1<<0),
PSW_EIE = (1<<1),
PSW_BIE = (1<<2),
PSW_ITLB = (1<<4),
PSW_EITLB = (1<<5),
PSW_BITLB = (1<<6),
PSW_DTLB = (1<<7),
PSW_EDTLB = (1<<8),
PSW_BDTLB = (1<<9),
PSW_USR = (1<<10),
PSW_EUSR = (1<<11),
PSW_BUSR = (1<<12),
};
/* TLBCTRL commands */
enum {
ITLB_FLUSH = 0x02,
DTLB_FLUSH = 0x03,
ITLB_UPDATE = 0x04,
DTLB_UPDATE = 0x05,
ITLB_INVALIDATE = 0x20,
DTLB_INVALIDATE = 0x21,
};
/* CSRs */
enum {
...
CSR_PSW = 0x1c,
CSR_TLBCTRL = 0x1d,
CSR_TLBVADDR = 0x1e,
CSR_TLBPADDR = 0x1f,
};