module tmu2_dpram #(
	parameter depth = 11, /* < log2 of the capacity in words */
	parameter width = 32
) (
	input sys_clk,
	input ce,

	input [depth-1:0] a,
	output [width-1:0] do,

	input [depth-1:0] wa,
	input we,
	input [width-1:0] di,
);

reg [width-1:0] ram[0:(1 << depth)-1];

reg [depth-1:0] ar;

always @(posedge sys_clk) begin
	if(ce) begin
		if(we)
			ram[w] <= di;
		ar <= a;
	end
end

assign do = ram[ar];

endmodule