1. 04[22:57] <wpyh> mcuelenaere: I saw some progress on the vx747 port
  2. [22:57] <wpyh> does RB now run on it?
  3. 01[22:57] <mcuelenaere> nah
  4. 01[22:57] <mcuelenaere> the MMU is killing me :/
  5. [22:58] <wpyh> why?
  6. 01[22:58] <mcuelenaere> I really hate it and just want to get rid of it
  7. 01[22:58] <mcuelenaere> it gives me TLB errors
  8. [22:58] <wpyh> AFAIK RB doesn't use the MMU
  9. 01[22:58] <mcuelenaere> exactly
  10. [22:58] <wpyh> scorche: well, maybe next time then
  11. 01[22:58] <mcuelenaere> MIPS uses a TLB with 32 items
  12. [22:59] <wpyh> or... should we make a MMU-less and MMU-ful RB versions?
  13. 01[22:59] <mcuelenaere> and whenever a memory location isn't in one of those, the processor does an interrupt requesting for a refill
  14. 01[22:59] <mcuelenaere> but the problem is I don't want to refill it
  15. 01[22:59] <mcuelenaere> + it seems to give TLB errors on the framebuffer :/
  16. 04[22:59] <wpyh> mcuelenaere: can we disable the MMU?
  17. 01[22:59] <mcuelenaere> I tried, but it didn't work
  18. 01[22:59] <mcuelenaere> if I just had some more documentation
  19. 06[22:59] * wpyh is not too familiar with that
  20. 01[22:59] <mcuelenaere> like JzRISC
  21. 01[23:00] <mcuelenaere> neither am I :/
  22. 01[23:00] <mcuelenaere> the docs I have document all the other chips in the SoC, but not the processor itself
  23. [23:00] <gevaerts> Am I the only one who doesn't see the point of FS#9346 ?
  24. 04[23:01] <wpyh> mcuelenaere: for the time being, can we ignore those interrupts?
  25. 01[23:02] <mcuelenaere> no, then all the others are ignored too
  26. 01[23:02] <mcuelenaere> I think
  27. 01[23:02] <mcuelenaere> and we need them
  28. 06[23:02] * wpyh doesn't understand why...
  29. 01[23:02] <mcuelenaere> you don't understand why we need interrupts?
  30. 01[23:02] <mcuelenaere> because a lot of code is based on it
  31. 01[23:03] <mcuelenaere> s/based/dependant/
  32. 01[23:03] <mcuelenaere> like the current_tick
  33. [23:03] <wpyh> uh, I mean
  34. [23:03] <wpyh> can we ignore all such interrupts (that are raised because of the TLB miss)
  35. [23:04] <gevaerts> Is this development talk?
  36. 01[23:04] <mcuelenaere> yes, perhaps this should be moved to #rockbox
  37. [23:04] <wpyh> gevaerts: more like a lesson in OS design
  38. [23:04] <wpyh> :p
  39. [23:04] <gevaerts> wpyh: make sure the resulting OS doesn't have a name with rocks in it?
  40. [23:04] <gevaerts> s/?/:)/
  41. [23:05] <wpyh> :p