1. from migen.fhdl import structure as f
  2. from migen.fhdl import verilog
  3.  
  4. class RoundRobin:
  5. def __init__(self, n):
  6. self.n = n
  7. self.bn = f.BitsFor(self.n-1)
  8. f.Declare(self, "request", f.BV(self.n))
  9. f.Declare(self, "grant", f.BV(self.bn))
  10.  
  11. def GetFragment(self):
  12. cases = []
  13. for i in range(self.n):
  14. switch = []
  15. for j in reversed(range(i+1,i+self.n)):
  16. t = j % self.n
  17. switch = [f.If(self.request[t],
  18. [f.Assign(self.grant, f.Constant(t, f.BV(self.bn)))],
  19. switch)]
  20. case = f.If(~self.request[i], switch)
  21. cases.append((f.Constant(i, f.BV(self.bn)), case))
  22. statement = f.Case(self.grant, cases)
  23. return f.Fragment(sync=[statement])
  24.  
  25. r = RoundRobin(5)
  26. frag = r.GetFragment()
  27. print(verilog.Convert(frag, {r.request, r.grant}))
  28.  
  29. ===============
  30.  
  31. /* Machine-generated using Migen */
  32. module top(
  33. input sys_clk,
  34. input sys_rst,
  35. input [4:0] Inst_request,
  36. output reg [2:0] Inst_grant
  37. );
  38.  
  39.  
  40. always @(posedge sys_clk) begin
  41. if (sys_rst) begin
  42. Inst_grant <= 3'd0;
  43. end else begin
  44. case (Inst_grant)
  45. 3'd0: begin
  46. if ((~Inst_request[0])) begin
  47. if (Inst_request[1]) begin
  48. Inst_grant <= 3'd1;
  49. end else begin
  50. if (Inst_request[2]) begin
  51. Inst_grant <= 3'd2;
  52. end else begin
  53. if (Inst_request[3]) begin
  54. Inst_grant <= 3'd3;
  55. end else begin
  56. if (Inst_request[4]) begin
  57. Inst_grant <= 3'd4;
  58. end
  59. end
  60. end
  61. end
  62. end
  63. end
  64. 3'd1: begin
  65. if ((~Inst_request[1])) begin
  66. if (Inst_request[2]) begin
  67. Inst_grant <= 3'd2;
  68. end else begin
  69. if (Inst_request[3]) begin
  70. Inst_grant <= 3'd3;
  71. end else begin
  72. if (Inst_request[4]) begin
  73. Inst_grant <= 3'd4;
  74. end else begin
  75. if (Inst_request[0]) begin
  76. Inst_grant <= 3'd0;
  77. end
  78. end
  79. end
  80. end
  81. end
  82. end
  83. 3'd2: begin
  84. if ((~Inst_request[2])) begin
  85. if (Inst_request[3]) begin
  86. Inst_grant <= 3'd3;
  87. end else begin
  88. if (Inst_request[4]) begin
  89. Inst_grant <= 3'd4;
  90. end else begin
  91. if (Inst_request[0]) begin
  92. Inst_grant <= 3'd0;
  93. end else begin
  94. if (Inst_request[1]) begin
  95. Inst_grant <= 3'd1;
  96. end
  97. end
  98. end
  99. end
  100. end
  101. end
  102. 3'd3: begin
  103. if ((~Inst_request[3])) begin
  104. if (Inst_request[4]) begin
  105. Inst_grant <= 3'd4;
  106. end else begin
  107. if (Inst_request[0]) begin
  108. Inst_grant <= 3'd0;
  109. end else begin
  110. if (Inst_request[1]) begin
  111. Inst_grant <= 3'd1;
  112. end else begin
  113. if (Inst_request[2]) begin
  114. Inst_grant <= 3'd2;
  115. end
  116. end
  117. end
  118. end
  119. end
  120. end
  121. 3'd4: begin
  122. if ((~Inst_request[4])) begin
  123. if (Inst_request[0]) begin
  124. Inst_grant <= 3'd0;
  125. end else begin
  126. if (Inst_request[1]) begin
  127. Inst_grant <= 3'd1;
  128. end else begin
  129. if (Inst_request[2]) begin
  130. Inst_grant <= 3'd2;
  131. end else begin
  132. if (Inst_request[3]) begin
  133. Inst_grant <= 3'd3;
  134. end
  135. end
  136. end
  137. end
  138. end
  139. end
  140. endcase
  141. end
  142. end
  143.  
  144. endmodule
  145.  
  146.