from migen.fhdl import structure as f
from migen.fhdl import verilog
class RoundRobin:
def __init__(self, n):
self.n = n
self.bn = f.BitsFor(self.n-1)
f.Declare(self, "request", f.BV(self.n))
f.Declare(self, "grant", f.BV(self.bn))
def GetFragment(self):
cases = []
for i in range(self.n):
switch = []
for j in reversed(range(i+1,i+self.n)):
t = j % self.n
switch = [f.If(self.request[t],
[f.Assign(self.grant, f.Constant(t, f.BV(self.bn)))],
switch)]
case = f.If(~self.request[i], switch)
cases.append((f.Constant(i, f.BV(self.bn)), case))
statement = f.Case(self.grant, cases)
return f.Fragment(sync=[statement])
r = RoundRobin(5)
frag = r.GetFragment()
print(verilog.Convert(frag, {r.request, r.grant}))
===============
/* Machine-generated using Migen */
module top(
input sys_clk,
input sys_rst,
input [4:0] Inst_request,
output reg [2:0] Inst_grant
);
always @(posedge sys_clk) begin
if (sys_rst) begin
Inst_grant <= 3'd0;
end else begin
case (Inst_grant)
3'd0: begin
if ((~Inst_request[0])) begin
if (Inst_request[1]) begin
Inst_grant <= 3'd1;
end else begin
if (Inst_request[2]) begin
Inst_grant <= 3'd2;
end else begin
if (Inst_request[3]) begin
Inst_grant <= 3'd3;
end else begin
if (Inst_request[4]) begin
Inst_grant <= 3'd4;
end
end
end
end
end
end
3'd1: begin
if ((~Inst_request[1])) begin
if (Inst_request[2]) begin
Inst_grant <= 3'd2;
end else begin
if (Inst_request[3]) begin
Inst_grant <= 3'd3;
end else begin
if (Inst_request[4]) begin
Inst_grant <= 3'd4;
end else begin
if (Inst_request[0]) begin
Inst_grant <= 3'd0;
end
end
end
end
end
end
3'd2: begin
if ((~Inst_request[2])) begin
if (Inst_request[3]) begin
Inst_grant <= 3'd3;
end else begin
if (Inst_request[4]) begin
Inst_grant <= 3'd4;
end else begin
if (Inst_request[0]) begin
Inst_grant <= 3'd0;
end else begin
if (Inst_request[1]) begin
Inst_grant <= 3'd1;
end
end
end
end
end
end
3'd3: begin
if ((~Inst_request[3])) begin
if (Inst_request[4]) begin
Inst_grant <= 3'd4;
end else begin
if (Inst_request[0]) begin
Inst_grant <= 3'd0;
end else begin
if (Inst_request[1]) begin
Inst_grant <= 3'd1;
end else begin
if (Inst_request[2]) begin
Inst_grant <= 3'd2;
end
end
end
end
end
end
3'd4: begin
if ((~Inst_request[4])) begin
if (Inst_request[0]) begin
Inst_grant <= 3'd0;
end else begin
if (Inst_request[1]) begin
Inst_grant <= 3'd1;
end else begin
if (Inst_request[2]) begin
Inst_grant <= 3'd2;
end else begin
if (Inst_request[3]) begin
Inst_grant <= 3'd3;
end
end
end
end
end
end
endcase
end
end
endmodule