coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
*sysinfo range: [000cf000,000cf730]
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=00
(1,0) link=02
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
core0 started: 01
started ap apicid: * AP 01started
* AP 03started
SBLink=01
NC node|link=01
NC node|link=02
busn=40
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x2
entering ht_optimize_link
pos=0xaa, unfiltered freq_cap=0x8075
pos=0xaa, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x7f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x0
entering ht_optimize_link
pos=0xca, unfiltered freq_cap=0x8075
pos=0xca, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x7f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 1, reset_needed=0x0
after optimize_link_read_pointers_chain, reset_needed=0x0
mcp55_num:01
ht reset -
coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
*sysinfo range: [000cf000,000cf730]
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=00
(1,0) link=02
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
core0 started: 01
started ap apicid: * AP 01started
* AP 03started
SBLink=01
NC node|link=01
NC node|link=02
busn=40
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x2
entering ht_optimize_link
pos=0xaa, unfiltered freq_cap=0x8075
pos=0xaa, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x7f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x0
entering ht_optimize_link
pos=0xca, unfiltered freq_cap=0x8075
pos=0xca, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x7f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 1, reset_needed=0x0
after optimize_link_read_pointers_chain, reset_needed=0x0
mcp55_num:01
Ram1.00
setting up CPU 00 northbridge registers
done.
Ram1.01
setting up CPU 01 northbridge registers
done.
Ram2.00
sdram_set_spd_registers: paramx :000cef28
DIMM socket 0, channel 0 SPD device is 0x50
DIMM socket 0, channel 1 SPD device is 0x51
DIMM socket 1, channel 0 SPD device is 0x52
DIMM socket 1, channel 1 SPD device is 0x53
DIMM socket 2, channel 0 SPD device is 0x00
DIMM socket 2, channel 1 SPD device is 0x00
DIMM socket 3, channel 0 SPD device is 0x00
DIMM socket 3, channel 1 SPD device is 0x00
sdram_set_spd_registers: dimm_mask=0x22
Common CAS latency bitfield: 0x38
Enabling dual channel memory
spd_enable_2channels: dimm_mask=0x22
spd_set_ram_size: dimm_mask=0x22
Registered
spd_handle_unbuffered_dimms: dimm_mask=0x22
1 min_cycle_time: 00000250
1.1 dimm_mask: 00000022
i: 00000000
1.1 dimm_mask: 00000022
i: 00000001
Channel 0 settings:
latencies: 00000038
index: 00000000
latency: 00000003
value1: 00000050
value2: 00000500
new_cycle_time: 00000500
new_latency: 00000003
index: 00000001
latency: 00000004
value1: 0000003d
value2: 00000375
new_cycle_time: 00000375
new_latency: 00000004
index: 00000002
latency: 00000005
value1: 00000030
value2: 00000300
new_cycle_time: 00000300
new_latency: 00000005
2 min_cycle_time: 00000300
2 min_latency: 00000005
Channel 1 settings:
latencies: 00000038
index: 00000000
latency: 00000003
value1: 00000050
value2: 00000500
new_cycle_time: 00000500
new_latency: 00000003
index: 00000001
latency: 00000004
value1: 0000003d
value2: 00000375
new_cycle_time: 00000375
new_latency: 00000004
index: 00000002
latency: 00000005
value1: 00000030
value2: 00000300
new_cycle_time: 00000300
new_latency: 00000005
2 min_cycle_time: 00000300
2 min_latency: 00000005
1.1 dimm_mask: 00000022
i: 00000002
1.1 dimm_mask: 00000022
i: 00000003
3 min_cycle_time: 00000300
3 min_latency: 00000005
4 min_cycle_time: 00000300
333MHz
333MHz
spd_set_memclk: dimm_mask=0x22
spd_set_dram_timing dimm socket: 00000001
trc
update_dimm_Trc: tRC (41) = 0000003c
update_dimm_Trc: tRC final value = 2400
update_dimm_Trc: clocks = 20
update_dimm_Trc: clocks after adjustment = 20
trcd
trrd
tras
update_dimm_Tras: 0 value= 0000002d
update_dimm_Tras: 1 value= 00000708
update_dimm_Tras: divisor= 00000078
update_dimm_Tras: clocks= 0000000f
trp
trtp
twr
tref
twtr
trfc
spd_set_dram_timing: dimm_mask=0x22
Interleaved
RAM end at 0x00400000 kB
Adjusting lower RAM end
Lower RAM end at 0x003f0000 kB
Ram2.01
sdram_set_spd_registers: paramx :000cef28
DIMM socket 0, channel 0 SPD device is 0x54
DIMM socket 0, channel 1 SPD device is 0x55
DIMM socket 1, channel 0 SPD device is 0x56
DIMM socket 1, channel 1 SPD device is 0x57
DIMM socket 2, channel 0 SPD device is 0x00
DIMM socket 2, channel 1 SPD device is 0x00
DIMM socket 3, channel 0 SPD device is 0x00
DIMM socket 3, channel 1 SPD device is 0x00
sdram_set_spd_registers: dimm_mask=0x22
Common CAS latency bitfield: 0x38
Enabling dual channel memory
spd_enable_2channels: dimm_mask=0x22
spd_set_ram_size: dimm_mask=0x22
Registered
spd_handle_unbuffered_dimms: dimm_mask=0x22
1 min_cycle_time: 00000250
1.1 dimm_mask: 00000022
i: 00000000
1.1 dimm_mask: 00000022
i: 00000001
Channel 0 settings:
latencies: 00000038
index: 00000000
latency: 00000003
value1: 00000050
value2: 00000500
new_cycle_time: 00000500
new_latency: 00000003
index: 00000001
latency: 00000004
value1: 0000003d
value2: 00000375
new_cycle_time: 00000375
new_latency: 00000004
index: 00000002
latency: 00000005
value1: 00000030
value2: 00000300
new_cycle_time: 00000300
new_latency: 00000005
2 min_cycle_time: 00000300
2 min_latency: 00000005
Channel 1 settings:
latencies: 00000038
index: 00000000
latency: 00000003
value1: 00000050
value2: 00000500
new_cycle_time: 00000500
new_latency: 00000003
index: 00000001
latency: 00000004
value1: 0000003d
value2: 00000375
new_cycle_time: 00000375
new_latency: 00000004
index: 00000002
latency: 00000005
value1: 00000030
value2: 00000300
new_cycle_time: 00000300
new_latency: 00000005
2 min_cycle_time: 00000300
2 min_latency: 00000005
1.1 dimm_mask: 00000022
i: 00000002
1.1 dimm_mask: 00000022
i: 00000003
3 min_cycle_time: 00000300
3 min_latency: 00000005
4 min_cycle_time: 00000300
333MHz
333MHz
spd_set_memclk: dimm_mask=0x22
spd_set_dram_timing dimm socket: 00000001
trc
update_dimm_Trc: tRC (41) = 0000003c
update_dimm_Trc: tRC final value = 2400
update_dimm_Trc: clocks = 20
update_dimm_Trc: clocks after adjustment = 20
trcd
trrd
tras
update_dimm_Tras: 0 value= 0000002d
update_dimm_Tras: 1 value= 00000708
update_dimm_Tras: divisor= 00000078
update_dimm_Tras: clocks= 0000000f
trp
trtp
twr
tref
twtr
trfc
spd_set_dram_timing: dimm_mask=0x22
Interleaved
RAM end at 0x00800000 kB
Handling memory mapped above 4 GB
Upper RAM end at 0x00800000 kB
Correcting memory amount mapped below 4 GB
Adjusting lower RAM end
Lower RAM end at 0x003f0000 kB
Ram3
ECC enabled
ECC enabled
Initializing memory: done
Initializing memory: done
Handling memory hole at 0x00300000 (default)
RAM end at 0x00900000 kB
Handling memory mapped above 4 GB
Upper RAM end at 0x00900000 kB
Correcting memory amount mapped below 4 GB
Adjusting lower RAM end
Lower RAM end at 0x00300000 kB
set DQS timing:RcvrEn:Pass1: 00
------Address debug: TrainRcvEn: buf_a:000ced20------
done
set DQS timing:DQSPos: 00
TrainDQSRdWrPos: buf_a:000ce9a0
TrainDQSPos: MutualCSPassW[48] :000ce878
TrainDQSPos: MutualCSPassW[48] :000ce878
TrainDQSPos: MutualCSPassW[48] :000ce878
TrainDQSPos: MutualCSPassW[48] :000ce878
TrainDQSPos: MutualCSPassW[48] :000ce878
TrainDQSPos: MutualCSPassW[48] :000ce878
coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
*sysinfo range: [000cf000,000cf730]
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=00
(1,0) link=02
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
core0 started: 01
started ap apicid: * AP 01started
* AP 03started
SBLink=01
NC node|link=01
NC node|link=02
busn=40
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x2
entering ht_optimize_link
pos=0xaa, unfiltered freq_cap=0x8075
pos=0xaa, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x7f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x
coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
*sysinfo range: [000cf000,000cf730]
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=00
(1,0) link=02
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
core0 started: 01
started ap apicid: * AP 01started
* AP 03started
SBLink=01
NC node|link=01
NC node|link=02
busn=40
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x2
entering ht_optimize_link
pos=0xaa, unfiltered freq_cap=0x8075
pos=0xaa, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x7f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x
coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
*sysinfo range: [000cf000,000cf730]
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=00
(1,0) link=02
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
core0 started: 01
started ap apicid: * AP 01started
* AP 03started
SBLink=01
NC node|link=01
NC node|link=02
busn=40
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x2
entering ht_optimize_link
pos=0xaa, unfiltered freq_cap=0x8075
pos=0xaa, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x7f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x
coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
*sysinfo range: [000cf000,000cf730]
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=00
(1,0) link=02
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
core0 started: 01
started ap apicid: * AP 01started
* AP 03started
SBLink=01
NC node|link=01
NC node|link=02
busn=40
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x2
entering ht_optimize_link
pos=0xaa, unfiltered freq_cap=0x8075
pos=0xaa, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x7f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x
coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
*sysinfo range: [000cf000,000cf730]
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=00
(1,0) link=02
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
core0 started: 01
started ap apicid: * AP 01started
* AP 03started
SBLink=01
NC node|link=01
NC node|link=02
busn=40
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x2
entering ht_optimize_link
pos=0xaa, unfiltered freq_cap=0x8075
pos=0xaa, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x7f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x
coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
*sysinfo range: [000cf000,000cf730]
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=00
(1,0) link=02
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
core0 started: 01
started ap apicid: * AP 01started
* AP 03started
SBLink=01
NC node|link=01
NC node|link=02
busn=40
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x2
entering ht_optimize_link
pos=0xaa, unfiltered freq_cap=0x8075
pos=0xaa, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x7f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x
coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
*sysinfo range: [000cf000,000cf730]
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=00
(1,0) link=02
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
core0 started: 01
started ap apicid: * AP 01started
* AP 03started
SBLink=01
NC node|link=01
NC node|link=02
busn=40
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x2
entering ht_optimize_link
pos=0xaa, unfiltered freq_cap=0x8075
pos=0xaa, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x7f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x