module
datapath
(
output
reg
[
31
:
15
]
p_high
,
output
reg
[
14
:
0
]
p_low
,
input
[
15
:
0
]
x
,
y
,
input
clk
)
;
// reset, start, x_ce, y_ce, y_load_en, p_reset,
//output done);
reg
[
15
:
0
]
q0
;
reg
[
15
:
0
]
q1
;
reg
[
15
:
0
]
and_output
;
reg
[
16
:
0
]
sum
,
prev_sum
;
reg
d_in
;
reg
[
3
:
0
]
count_er
;
initial
begin
count_er
<=
0
;
sum
<=
1
7'b0
;
and_output
<=
0
;
end
always
@*
begin
and_output
<=
q0
[
count_er
]
&
q1
;
sum
<=
and_output
+
sum
;
d_in
<=
p_high
[
15
]
;
end
always
@
(
posedge
clk
)
begin
q0
<=
y
;
q1
<=
x
;
p_high
<=
sum
;
p_low
[
14
]
<=
d_in
;
p_low
<=
p_low
>>
1
;
count_er
<=
count_er
+
1
;
end
endmodule