uint8_t adc_control(int channel) {
/* clkgate - reset first, then enable */
__REG_SET(HW_LRADC_CTRL0) = __BLOCK_SFTRST;
__REG_CLR(HW_LRADC_CTRL0) = __BLOCK_CLKGATE | __BLOCK_SFTRST;
/* divide by 2 */
__REG_SET(HW_LRADC_CTRL2) = HW_LRADC_CTRL2__DIVIDE_BY_TWO(1);
/* accumulate & samples */
HW_LRADC_CHx(channel) = (0 << HW_LRADC_CHx__ACCUMULATE) | (1 << HW_LRADC_CHx__NUM_SAMPLES_BP);
/* schedule */
__REG_CLR(HW_LRADC_CTRL1) = HW_LRADC_CTRL1__LRADCx_IRQ(channel);
__REG_SET(HW_LRADC_CTRL0) = HW_LRADC_CTRL0__SCHEDULE(channel);
/* wait */
while(!(HW_LRADC_CTRL1 & HW_LRADC_CTRL1__LRADCx_IRQ(channel)))
{
uart_tx("waiting for ADC completition...\r\n");
};
/* get value */
return (HW_LRADC_CHx(channel) & HW_LRADC_CHx__VALUE_BM) >> HW_LRADC_CHx__VALUE_BP;
}