PCIe event definitions (each event counts as a transfer):
   PCIe read events (PCI devices reading from memory - application writes to disk/network/PCIe device):
     PCIePRd   - PCIe UC read transfer (partial cache line)
     PCIeRdCur* - PCIe read current transfer (full cache line)
         On Haswell Server PCIeRdCur counts both full/partial cache lines
     RFO*      - Demand Data RFO
     CRd*      - Demand Code Read
     DRd       - Demand Data Read
     PCIeNSWr  - PCIe Non-snoop write transfer (partial cache line)
     PRd       - MMIO Read [Haswell Server only: PL verify this on IVT] (Partial Cache Line)
   PCIe write events (PCI devices writing to memory - application reads from disk/network/PCIe device):
     PCIeWiLF  - PCIe Write transfer (non-allocating) (full cache line)
     PCIeItoM  - PCIe Write transfer (allocating) (full cache line)
     PCIeNSWr  - PCIe Non-snoop write transfer (partial cache line)
     PCIeNSWrF - PCIe Non-snoop write transfer (full cache line)
     ItoM      - PCIe write full cache line
     RFO       - PCIe parial Write
     WiL       - MMIO Write (Full/Partial)

 * - NOTE: Depending on the configuration of your BIOS, this tool may report '0' if the message
           has not been selected.

Number of physical cores: 8
Number of logical cores: 8
Number of online logical cores: 8
Threads (logical cores) per physical core: 1
Num sockets: 1
Physical cores per socket: 8
Core PMU (perfmon) version: 3
Number of core PMU generic (programmable) counters: 8
Width of generic (programmable) counters: 48 bits
Number of core PMU fixed counters: 3
Width of fixed counters: 48 bits
Nominal core frequency: 3200000000 Hz
Package thermal spec power: 135 Watt; Package minimum power: 39 Watt; Package maximum power: 270 Watt;
2 memory controllers detected with total number of 5 channels.

Detected Intel(R) Xeon(R) CPU E5-2667 v3 @ 3.20GHz "Intel(r) microarchitecture codename Haswell-EP/EN/EX"
Update every 1 seconds
delay_ms: 84