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halfadder_tb

By: a guest on Aug 1st, 2012  |  syntax: VHDL  |  size: 0.77 KB  |  hits: 23  |  expires: Never
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  1. LIBRARY IEEE;
  2. USE IEEE.STD_LOGIC_1164.ALL;
  3. USE IEEE.NUMERIC_STD.ALL;
  4.  
  5. entity halfadder_tb is
  6. end halfadder_tb;
  7.  
  8. architecture behavioral of halfadder_tb is
  9.  
  10. component HALFADDER
  11.     port(A, B: in STD_LOGIC;
  12.     SUM, CARRY: out STD_LOGIC);
  13. end component;
  14.  
  15. signal AT, BT, SUMT, CARRYT: STD_LOGIC :='0';
  16.  
  17. begin
  18.  
  19.     dut: HALFADDER port map(A => AT,
  20.                             B => BT,
  21.                             SUM => SUMT,
  22.                             CARRY => CARRYT);
  23.    
  24.     test: process
  25.      
  26.     begin
  27.    
  28.     AT <= '0'; BT <= '0';
  29.     wait for 100 nS;
  30.     AT <= '1'; BT <= '0';
  31.     wait for 100 nS;
  32.     AT <= '0'; BT <= '1';
  33.     wait for 100 nS;
  34.     AT <= '1'; BT <= '1';
  35.     wait for 100 nS;
  36.    
  37.   end process test;
  38.    
  39. end behavioral;
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