D33 VHDL Paste

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity asdf is
	PORT (
    clk      : IN  STD_LOGIC;
    ena      : IN  STD_LOGIC;
    rst      : IN  STD_LOGIC;
    data_in  : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
    data_out : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
    );
end asdf;

architecture Behavioral of asdf is
  SIGNAL reg0 : std_logic_vector(8 DOWNTO 0);
  SIGNAL data : std_logic_vector(2 DOWNTO 0);
begin

  data     <= data_in;

  PROCESS (clk, rst) IS
  BEGIN  -- PROCESS
    IF rst = '1' THEN                   -- asynchronous reset (active high)
      reg0 <= "000000000";
    ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
      reg0 <= reg0(5 downto 0) & data_in;
      data_out <= reg0;
    END IF;
  END PROCESS;

end Behavioral;