Untitled

module ddd_ff(q, d, clk, clear);

 

  output q;

  input d, clk, clear;

  reg q;

 

  initial

  begin

  q = 1'b0;

  end

 

  always@(negedge clk or posedge clear)

  if(clear)

    q <= 1'b0;

  else

  q <= d;

endmodule  

 

module mod_5 (Q, clock, clear);

 

  output [2:0] Q;

  input clock;

  input clear;

 

  wire [2:0] Q_not;

  wire CLEAR;

 

initial

begin

  $monitor( " clear : %d clock: %d Q1 : %b, Q2: %b, Q3: %b, ~Q[0]: %b, ~Q[1]: %b ~Q[2]: %b",clear ,clock, Q[0], Q[1], Q[2], Q_not[0], Q_not[1], Q_not[2]);

end

 

  assign CLEAR = (Q[0] & Q[2]);

  assign Q_not[0] = ~Q[0];

  assign Q_not[1] = ~Q[1];

  assign Q_not[2] = ~Q[2];

 

  ddd_ff t0(Q[0], Q_not[0], clock, CLEAR);

  ddd_ff t1(Q[1], Q_not[1], Q[0], CLEAR);

  ddd_ff t2(Q[2], Q_not[2], Q[1], CLEAR);

 

endmodule