
Untitled
By: a guest on
Jul 11th, 2012 | syntax:
VeriLog | size: 0.70 KB | hits: 31 | expires: Never
`timescale 1ns / 1ps
module Pipeline(out0, out1, inA, inB);
integer i = 0;
function funcao;
input a, b, c;
begin
if(a === 1'bX | b === 1'bX)
begin
if(c === 0)
funcao = 1;
else
funcao = 0;
i = 1;
end
else if(a === b)
begin
funcao = a;
end
else if(funcao === 1'bX)
begin
funcao = 1;
end
$display($time, " - %b - A = %b B = %b OUT = %b - %d", c, a, b, funcao, i);
i = 0;
end
endfunction
input inA, inB;
output out0, out1;
reg out0, out1;
initial begin
out0 = 1;
out1 = 0;
end
always @ (inA)
begin
out0 = funcao(inA, !out1, 0);
end
always @ (inB)
begin
out1 = funcao(out0, !inB, 1);
end
endmodule