Clock Code

library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use UNISIM.VComponents.all;

entity Clock is
    Port ( PRESET : in std_logic;
              CLR : in std_logic;
              clk : out std_logic);
end Clock;

architecture behavioral of Clock is

    constant D : std_logic := '0';  -- Data input
    constant G : std_logic := '0';  -- Gate input
    constant GE : std_logic := '0'; -- Gate Enable

begin

     LDCPEInstance : LDCPE generic map (INIT => '0') -- Initial value of the latch
     port map (
        Q => clk,       -- Data output
        CLR => CLR,     -- Asynchronous clear/reset input
        D => D,         -- Data input is grounded
        G => G,         -- Gate input is grounded
        GE => GE,       -- Gate Enable input is grounded
        PRE => PRESET   -- Asynchronous preset/set input
     );

end behavioral;