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-- Company:
-- Engineer:
--
-- Create Date:    19:10:01 05/12/2016
-- Design Name:
-- Module Name:    regtot - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity regtot is
    Port ( t_ld: in STD_LOGIC;
             t_clr : in STD_LOGIC;
             s_somador :in STD_LOGIC_VECTOR ( 3 downto 0);
             t_saida : out STD_LOGIC_VECTOR (3 downto 0));

end regtot;


architecture Behavioral of regtot is
begin

registrador: process (t_clr, t_ld)
begin
    if t_clr = '1' then
        t_saida <= "0000" ;
    elsif rising_edge(t_ld) then
         t_saida<= s_somador;
    end if;
end process;


end Behavioral;