Untitled

//******************************************************************************
//  MSP430F22x4 Demo - USCI_B0 I2C Master Interface to DAC8571, Write
//
//  Description: Using UCB0TXIE, a continuous sine wave is output to the
//  external DAC using a 16-point look-up table. Only one start condition
//  is executed. Data is handled by the ISR and the CPU is normally in LPM0.
//  ACLK = n/a, MCLK = SMCLK = BRCLK = default DCO = ~1.2MHz
//

//               MSP430F22x4                 AD5622
//           --------------               -----------
//          |P3.1/UCB0SDA | P18 <---->  3 | SDA     |
//          |P3.2/UCB0SCL | P15 ----->  2 | SCL     |
//          |        GND  | P1        5/1 | GND     |
//          |         VCC | P2          4 | VDD     |
//          --------------                -----------
//
//
//  AD5622 I2C address = 0x0F (A0 = GND)
//
//  Andreas Dannenberg
//  Texas Instruments Inc.
//  March 2006
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.41A
//******************************************************************************
#include "msp430x22x4.h"
static unsigned char ByteCtr=0;
const unsigned char Sine_Tab[] =            // 16 Point 16-bit Sine Table
{
  0x0F,                                     // MSB Word 0
  0xFF,                                     // LSB
  0x00,                                     // MSB Word 1
  0x00,                                     // LSB
};
void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop Watchdog Timer
  P1DIR |= 0x03;
  P1OUT = 0x02;
  P3SEL |= 0x06;                            // Sets P3.1 to UCB0SDA, 3.2 to UCB0SCL
  UCB0CTL1 |= UCSWRST;                      // Keep USCI in reset pg547
  UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC;     // I2C Master, synchronous mode. pg546
  UCB0CTL1 = UCSSEL_2 + UCSWRST;            // Selects the SMCLK and keeps USCI in reset pg547
  UCB0BR0 = 12;                             // Sets data clock to ~100KHz pg541. SMCLK/11 pg289   //low bit
  UCB0BR1 = 0;                              // Sets data clock to ~100KHz pg541. SMCLK/12 pg289   //high bit
  UCB0I2CSA = 0x0F;                         // Set slave address
  UCB0CTL1 &= ~UCSWRST;                     // Bring USCI out of reset
  IE2 |= UCB0TXIE;                          // Interrupt enabled. pg516
  UCB0CTL1 |= UCTR + UCTXSTT;               // Sets transmit and sends START condition pg547
  while(1){
  __bis_SR_register(CPUOFF + GIE);          // Enter LPM0 w/ interrupts
  }
}

// USCI_B0 Data ISR
#pragma vector = USCIAB0TX_VECTOR
__interrupt void USCIAB0TX_ISR(void)
{
  P1OUT |= 0x01;
  UCB0TXBUF = Sine_Tab[ByteCtr++];          // Transmit data byte
  ByteCtr &= 0x01;                          // Do not exceed table
  P1OUT ^= 0x01;
}