module recursion #(parameter SIZE = 8)(
  input wire [32*SIZE - 1:0] a ,
  output reg [31: 0] out,
  input wire clk
);
wire [31:0] out0,out1;

generate
  if(SIZE == 1) begin
    assign out0[31:0] = a[31:0];
    assign out1[31:0] = 32'b0;
  end else if(SIZE == 2) begin
    assign out0[31:0] = a[31:0];
    assign out1[31:0] = a[63:32];
  end else begin
    recursion #(SIZE / 2)  re0(
      .a(a[32*(SIZE / 2) - 1:0]),
      .clk( clk),
      .out(out0));
    recursion #(SIZE - SIZE / 2) re1 (
      .a(a[32*SIZE - 1:32*(SIZE / 2)]) ,
      .clk( clk),
      .out(out1) );
  end
endgenerate

always @ (posedge clk) begin
  out <= out0 + out1;
end
endmodule