EDA ASSIGNMENT

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY source is
port(i, reset: IN bit;
     o: OUT bit_vector( 1 downto 0);
     clk: IN bit);


END ENTITY source;
ARCHITECTURE fsm of source IS
TYPE state_type IS(a, b, c, d);
SIGNAL current_state, next_state: state_type;
BEGIN
CS: PROCESS (clk, reset) IS
BEGIN
IF reset = '1' THEN current_state <= a;
ELSIF  clk = '1' AND clk'event THEN  current_state <= next_state;
END IF;
END PROCESS CS;
Operation: PROCESS (current_state, i)
BEGIN
CASE current_state IS
WHEN a =>
IF i='1' THEN
o <= "11";
next_state <= b;
ELSE
o <="00";
next_state <= a;
END IF;
WHEN b =>
IF i='1' THEN
o <= "01";
next_state <= d;
ELSE
o <="10";
next_state <= c;
END IF;
WHEN c =>
IF i='1' THEN
o <= "00";
next_state <= b;
ELSE
o <="11";
next_state <= a;
END IF;
WHEN d =>
IF i='1' THEN
o <= "10";
next_state <= d;
ELSE
o <="01";
next_state <= c;
END IF;
END CASE;
END PROCESS Operation;
END ARCHITECTURE fsm;
ENTITY testbench IS
END ENTITY testbench;
ARCHITECTURE arch OF testbench IS

COMPONENT source
PORT(i, reset: IN bit;
     o: OUT bit_vector( 1 downto 0);
     clk: IN bit);
END COMPONENT source;
FOR DUT: source USE ENTITY work.source(fsm);
SIGNAL reset: bit;
SIGNAL i : bit;
SIGNAL clk:  bit;
SIGNAL o: bit_vector( 1 downto 0);
BEGIN
DUT: source port map(i, Reset, O, Clk);
SG: PROCESS IS
BEGIN
Reset <= '1';
clk <='0';
Wait FOR 20 ns;

i<='1';
Wait FOR 20 ns;
clk<='1';
Wait FOR 20 ns;
assert o= "11";
REPORT "Reset error"
SEVERITY warning;

clk <= '0';
i <='0';
WAIT FOR 20 ns;

clk<= '1';
assert o="10"
REPORT "Reset error"
SEVERITY warning;



clk<='0';
i<='0';
WAIT FOR 20 ns;

clk<='1';
assert o = "11";
REPORT "Reset error"
SEVERITY warning;


clk<='0';
i<='1';
WAIT FOR 20 ns;


clk<='1';
assert o = "11";
REPORT "Reset error"
SEVERITY warning;

clk<='0';
i<='1';
WAIT FOR 20 ns;

clk <='1';
assert o= "00";
REPORT "Reset error"
SEVERITY warning;













END PROCESS SG;
END ARCHITECTURE arch;
--Name: Bassem Tarek Ahmed Mohamed