[mw@thanatos test]$ make sim_dtlb
iverilog -o tb_lm32 tb_lm32.v lm32_include.v ../rtl/lm32_adder.v ../rtl/lm32_addsub.v ../rtl/lm32_cpu.v ../rtl/lm32_dcache.v ../rtl/lm32_debug.v ../rtl/lm32_decoder.v ../rtl/lm32_dp_ram.v ../rtl/lm32_icache.v ../rtl/lm32_instruction_unit.v ../rtl/lm32_interrupt.v ../rtl/lm32_jtag.v ../rtl/lm32_load_store_unit.v ../rtl/lm32_logic_op.v ../rtl/lm32_mc_arithmetic.v ../rtl/lm32_multiplier.v ../rtl/lm32_ram.v ../rtl/lm32_shifter.v ../rtl/lm32_itlb.v ../rtl/lm32_dtlb.v ../rtl/lm32_top.v
VCD info: dumpfile tb_lm32.vcd opened for output.
DTLB STATE MACHINE RESET
ITLB STATE MACHINE RESET
ITLB STATE MACHINE RESET
DTLB STATE MACHINE RESET
stack == 0x440070B4
mapping 0x44002001->0x44001001 in slot 9 [0x44003d9c]
stack == 0x440070B4
mapping 0x44000001->0x44003001 in slot 8 [0x44003d90]
stack == 0x440070B4
mapping 0x44007001->0x44007001 in slot 7 [0x44003d84]
stack == 0x440070B4
mapping 0x44006001->0x44006001 in slot 6 [0x44003d78]
stack == 0x440070C4
addr == 0x44002004
[MMU OFF] *(0x44002004) == 0x00010203
[MMU ON] *(0x44002004) == 0x00010203
[MMU OFF] *(0x44001004) == 0x469303AC
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 00 : PASS
addr == 0x44002008
[MMU OFF] *(0x44002008) == 0x01020304
[MMU ON] *(0x44002008) == 0x01020304
[MMU OFF] *(0x44001008) == 0x78014400
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 01 : PASS
addr == 0x4400200C
[MMU OFF] *(0x4400200C) == 0x02030405
[MMU ON] *(0x4400200C) == 0x02030405
[MMU OFF] *(0x4400100C) == 0x38213690
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 02 : PASS
addr == 0x44002010
[MMU OFF] *(0x44002010) == 0x03040506
[MMU ON] *(0x44002010) == 0x03040506
[MMU OFF] *(0x44001010) == 0xFBFFFC9E
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 03 : PASS
addr == 0x44002014
[MMU OFF] *(0x44002014) == 0x04050607
[MMU ON] *(0x44002014) == 0x04050607
[MMU OFF] *(0x44001014) == 0x35AD0001
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 04 : PASS
addr == 0x44002018
[MMU OFF] *(0x44002018) == 0x05060708
[MMU ON] *(0x44002018) == 0x05060708
[MMU OFF] *(0x44001018) == 0x78014400
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 05 : PASS
addr == 0x4400201C
[MMU OFF] *(0x4400201C) == 0x06070809
[MMU ON] *(0x4400201C) == 0x06070809
[MMU OFF] *(0x4400101C) == 0x78034400
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 06 : PASS
addr == 0x44002020
[MMU OFF] *(0x44002020) == 0x0708090A
[MMU ON] *(0x44002020) == 0x0708090A
[MMU OFF] *(0x44001020) == 0x382137F0
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 07 : PASS
addr == 0x44002024
[MMU OFF] *(0x44002024) == 0x08090A0B
[MMU ON] *(0x44002024) == 0x08090A0B
[MMU OFF] *(0x44001024) == 0x386337F4
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 08 : PASS
addr == 0x44002028
[MMU OFF] *(0x44002028) == 0x090A0B0C
[MMU ON] *(0x44002028) == 0x090A0B0C
[MMU OFF] *(0x44001028) == 0x28330000
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 09 : PASS
addr == 0x4400202C
[MMU OFF] *(0x4400202C) == 0x0A0B0C0D
[MMU ON] *(0x4400202C) == 0x0A0B0C0D
[MMU OFF] *(0x4400102C) == 0x28720000
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 10 : PASS
addr == 0x44002030
[MMU OFF] *(0x44002030) == 0x0B0C0D0E
[MMU ON] *(0x44002030) == 0x0B0C0D0E
[MMU OFF] *(0x44001030) == 0x91605800
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 11 : PASS
addr == 0x44002034
[MMU OFF] *(0x44002034) == 0x0C0D0E0F
[MMU ON] *(0x44002034) == 0x0C0D0E0F
[MMU OFF] *(0x44001034) == 0x396B0040
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 12 : PASS
addr == 0x44002038
[MMU OFF] *(0x44002038) == 0x0D0E0F10
[MMU ON] *(0x44002038) == 0x0D0E0F10
[MMU OFF] *(0x44001038) == 0xD16B0000
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 13 : PASS
addr == 0x4400203C
[MMU OFF] *(0x4400203C) == 0x0E0F1011
[MMU ON] *(0x4400203C) == 0x0E0F1011
[MMU OFF] *(0x4400103C) == 0x98000000
[MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
Test n° 14 : PASS
TOTAL : 15/15 successes | 0/15 failures
^C** VVP Stop(0) **
** Flushing output streams.
** Current simulation time is 3798545 ticks.
> finish
** Continue **

[mw@thanatos test]$