library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity KBD_decode is
    Port ( clk : in STD_LOGIC;
	  DataIn : in  STD_LOGIC_VECTOR (7 downto 0);
           Enable : in  STD_LOGIC;
           DataOut : out  STD_LOGIC_VECTOR (15 downto 0));
end KBD_decode;

architecture Behavioral of KBD_decode is

signal reg : std_logic_vector (15 downto 0);
signal temp : std_logic_vector(3 downto 0);
signal checkf0 : std_logic_vector(7 downto 0);
signal keyrealase : std_logic;
begin

checkf0 <= DataIn when rising_edge(clk) and enable = '1';

with DataIn select
temp <=  '1' & x"0" when x"45",
			'1' &	x"1" when x"16",
			'1' & x"2" when x"1E",
			'1' & x"3" when x"26",
			'1' & x"4" when x"25",
			'1' & x"5" when x"2E",
			'1' & x"6" when x"36",
			'1' & x"7" when x"3D",
			'1' & x"8" when x"3E",
			'1' & x"9" when x"49",
			'1' & x"A" when x"1C",
			'1' & x"B" when x"32",
			'1' & x"C" when x"21",
			'1' & x"D" when x"23",
			'1' & x"E" when x"24",
			'1' & x"F" when x"2B",
			'0' & "----" when others;

		process (clk, Enable,F0,E0,DataIn,reg)
		begin
					if rising_edge(clk) then
						if Enable = '1' then
									if checkf0 = x"f0" then
										reg <= reg(15 downto 4) & temp;
									end if;
						end if;
					end if;
		end process;

		DataOut <= reg;




end Behavioral;