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Oct 31st, 2012
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VHDL 3.72 KB | None | 0 0
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3.  
  4. --library work;
  5. --use work.car_pkg.all;
  6.  
  7.  
  8. entity knight_rider2 is
  9.     port (  clk, resetn, clock_button : in std_logic;
  10.         led1, led2, led3, led4, led5, led6, led7, led8,
  11.         led9, led10, led11, led12, led13, led14, led15 : out std_logic);
  12. end entity knight_rider2;
  13.  
  14.  
  15.  
  16. architecture fsm of knight_rider2 is
  17.     type state_types is (start, forward1, forward2, forward3,
  18.     forward4, forward5, forward6, forward7, forward8, forward9,
  19.     forward10,forward11,forward12, forward13, forward14);
  20.    
  21.     variable fsm_pulse : boolean := false;
  22.     variable divider: integer := 2;
  23.     variable counter : integer := 0;
  24.     signal state: state_types;
  25.     signal led_states : std_logic_vector(14 downto 0);
  26.  
  27. begin
  28.            
  29.          count : process(clk, resetn, clock_button)
  30.             begin
  31.                 if clock_button = '0' then
  32.                 counter   := 0;
  33.             fsm_pulse := false;
  34.                 else
  35.                 if rising_edge(clk) then
  36.             counter     := counter + 1;
  37.                 fsm_pulse   := false;
  38.             if counter = divider then
  39.                 fsm_pulse := true;
  40.                 counter   := 0;
  41.                 end if;
  42.             end if;
  43.             end if;
  44.             end process;   
  45.  
  46.  
  47.     combined_next_current: process (clk, resetn, clock_button)
  48.     begin
  49.         if (resetn = '0') then
  50.             state <= start;
  51.         elsif rising_edge(clk) then
  52.             if fsm_pulse = true then
  53.             case state is
  54.  
  55.                 when start =>
  56.                     state <= forward1;
  57.  
  58.                 when forward1 =>               
  59.                     state <= forward2;             
  60.  
  61.  
  62.                 when forward2 =>                   
  63.                         state <= forward3;             
  64.  
  65.                 when forward3 =>           
  66.                         state <= forward4;             
  67.  
  68.                 when forward4 =>                   
  69.                         state <= forward5;                 
  70.  
  71.  
  72.                 when forward5 =>               
  73.                         state <= forward6;                 
  74.  
  75.  
  76.                 when forward6 =>                   
  77.                         state <= forward7;                 
  78.  
  79.  
  80.                 when forward7 =>               
  81.                             state <= forward8;             
  82.  
  83.                 when forward8 =>                   
  84.                             state <= forward9;     
  85.  
  86.  
  87.                 when forward9 =>                   
  88.                             state <= forward10;                    
  89.  
  90.                 when forward10 =>                      
  91.                             state <= forward11;
  92.  
  93.  
  94.                 when forward11 =>                  
  95.                             state <= forward12;                
  96.  
  97.  
  98.                 when forward12 =>                      
  99.                             state <= forward13;
  100.  
  101.  
  102.                 when forward13 =>                      
  103.                             state <= forward14;
  104.  
  105.  
  106.  
  107.                 when forward14 => state <=start;
  108.  
  109.                 when others =>
  110.                 state <= forward1;
  111.  
  112.             end case;
  113.         end if;
  114.         end if;
  115.     end process;
  116.  
  117.  
  118.     --combinational output logic
  119.  
  120.     --internal signal to control state machine transistions
  121.  
  122.  
  123.     led_select : process(state)
  124. begin
  125.   case state is
  126.     when forward1 =>
  127.      led_states <= "000000000000011";
  128.      when forward2 =>
  129.      led_states <= "000000000000110";
  130.     when forward3 =>
  131.      led_states <= "000000000001100";
  132.     when forward4 =>
  133.      led_states <= "000000000011000";
  134.      when forward5 =>
  135.      led_states <= "000000000110000";
  136.      when forward6 =>
  137.      led_states <= "000000001100000";
  138.      when forward7 =>
  139.      led_states <= "000000011000000";
  140.      when forward8 =>
  141.      led_states <= "000000110000000";
  142.      when forward9 =>
  143.      led_states <= "000001100000000";
  144.      when forward10 =>
  145.      led_states <= "000011000000000";
  146.      when forward11=>
  147.      led_states <= "000110000000000";
  148.      when forward12=>
  149.      led_states <= "001100000000000";
  150.      when forward13=>
  151.      led_states <= "011000000000000";
  152.      when forward14=>
  153.      led_states <= "110000000000000";
  154.      when others =>
  155.      led_states <= "100000000000001";
  156.    
  157.   end case;
  158. end process;
  159.  
  160. led1 <= led_states(0);
  161. led2 <= led_states(1);
  162. led3 <= led_states(2);
  163. led4 <= led_states(3);
  164. led5 <= led_states(4);
  165.  
  166. led6 <= led_states(5);
  167. led7 <= led_states(6);
  168. led8 <= led_states(7);
  169. led9 <= led_states(8);
  170. led10 <= led_states(9);
  171.  
  172. led11 <= led_states(10);
  173. led12 <= led_states(11);
  174. led13 <= led_states(12);
  175. led14 <= led_states(13);
  176. led15 <= led_states(14);
  177.  
  178.  
  179.  
  180.  
  181.              
  182. end;
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