library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.std_logic_arithext.all;


-- datapath entity
entity sincx_ins is
port(
     dataa                  : in  std_logic_vector(31 downto 0);
     datab                  : in  std_logic_vector(31 downto 0);
     start                  : in  std_logic;
     clk_en                 : in  std_logic;
     result                 : out std_logic_vector(31 downto 0);
     done                   : out std_logic;
     RST                    : in  std_logic;
     CLK                    : in  std_logic
);
end sincx_ins;


architecture RTL of sincx_ins is
-- signal declaration
signal full0              : std_logic_vector(31 downto 0);
signal full0_wire         : std_logic_vector(31 downto 0);
signal full1              : std_logic_vector(31 downto 0);
signal full1_wire         : std_logic_vector(31 downto 0);
signal full2              : std_logic_vector(31 downto 0);
signal full2_wire         : std_logic_vector(31 downto 0);
signal full3              : std_logic_vector(31 downto 0);
signal full3_wire         : std_logic_vector(31 downto 0);
signal tap0               : std_logic_vector(31 downto 0);
signal tap0_wire          : std_logic_vector(31 downto 0);
signal tap1               : std_logic_vector(31 downto 0);
signal tap1_wire          : std_logic_vector(31 downto 0);
signal tap2               : std_logic_vector(31 downto 0);
signal tap2_wire          : std_logic_vector(31 downto 0);
signal tap3               : std_logic_vector(31 downto 0);
signal tap3_wire          : std_logic_vector(31 downto 0);
signal op_phase0          : std_logic_vector(31 downto 0);
signal op_phase1          : std_logic_vector(31 downto 0);
signal op_phase2          : std_logic_vector(31 downto 0);
signal op_phase3          : std_logic_vector(31 downto 0);
signal Yinp               : std_logic_vector(31 downto 0);
signal Yinp_wire          : std_logic_vector(31 downto 0);
signal Xinp               : std_logic_vector(31 downto 0);
signal Xinp_wire          : std_logic_vector(31 downto 0);
signal datap              : std_logic_vector(31 downto 0);
signal datap_wire         : std_logic_vector(31 downto 0);
signal streg              : std_logic;
signal streg_wire         : std_logic;
signal dnreg              : std_logic;
signal dnreg_wire         : std_logic;
signal sig_0              : std_logic;
signal sig_1              : std_logic;
signal sig_2              : std_logic;
signal sig_3              : std_logic;
signal sig_4              : std_logic_vector(31 downto 0);
signal sig_5              : std_logic_vector(31 downto 0);
signal sig_6              : std_logic_vector(31 downto 0);
signal sig_7              : std_logic_vector(31 downto 0);
signal sig_8              : std_logic_vector(31 downto 0);
signal sig_9              : std_logic_vector(31 downto 0);
signal sig_10             : std_logic_vector(31 downto 0);
signal sig_11             : std_logic_vector(63 downto 0);
signal sig_12             : std_logic_vector(31 downto 0);
signal sig_13             : std_logic_vector(63 downto 0);
signal sig_14             : std_logic_vector(63 downto 0);
signal sig_15             : std_logic_vector(31 downto 0);
signal sig_16             : std_logic_vector(63 downto 0);
signal sig_17             : std_logic_vector(63 downto 0);
signal sig_18             : std_logic_vector(31 downto 0);
signal sig_19             : std_logic_vector(63 downto 0);
signal sig_20             : std_logic_vector(63 downto 0);
signal sig_21             : std_logic_vector(31 downto 0);
signal sig_22             : std_logic_vector(63 downto 0);
signal sig_23             : std_logic_vector(31 downto 0);
signal sig_24             : std_logic_vector(63 downto 0);
signal sig_25             : std_logic_vector(63 downto 0);
signal sig_26             : std_logic_vector(31 downto 0);
signal sig_27             : std_logic_vector(63 downto 0);
signal sig_28             : std_logic_vector(63 downto 0);
signal sig_29             : std_logic_vector(31 downto 0);
signal sig_30             : std_logic_vector(63 downto 0);
signal sig_31             : std_logic_vector(63 downto 0);
signal sig_32             : std_logic_vector(31 downto 0);
signal sig_33             : std_logic_vector(63 downto 0);
signal sig_34             : std_logic_vector(31 downto 0);
signal sig_35             : std_logic_vector(63 downto 0);
signal sig_36             : std_logic_vector(63 downto 0);
signal sig_37             : std_logic_vector(31 downto 0);
signal sig_38             : std_logic_vector(63 downto 0);
signal sig_39             : std_logic_vector(63 downto 0);
signal sig_40             : std_logic_vector(31 downto 0);
signal sig_41             : std_logic_vector(63 downto 0);
signal sig_42             : std_logic_vector(63 downto 0);
signal sig_43             : std_logic_vector(31 downto 0);
signal sig_44             : std_logic_vector(63 downto 0);
signal sig_45             : std_logic_vector(31 downto 0);
signal sig_46             : std_logic_vector(63 downto 0);
signal sig_47             : std_logic_vector(63 downto 0);
signal sig_48             : std_logic_vector(31 downto 0);
signal sig_49             : std_logic_vector(63 downto 0);
signal sig_50             : std_logic_vector(63 downto 0);
signal sig_51             : std_logic_vector(31 downto 0);
signal sig_52             : std_logic_vector(63 downto 0);
signal sig_53             : std_logic_vector(63 downto 0);
signal done_int           : std_logic;
signal result_int         : std_logic_vector(31 downto 0);
signal sig_54             : std_logic;
signal sig_55             : std_logic;


-- lookup table declaration
Type rom_table_0 is Array (Natural range <>) of std_logic_vector(31 downto 0);
constant c0 : rom_table_0 := (
          B"00000000000000000000000000000000",
          B"11111111111111111111011111000100",
          B"11111111111111111111001001101011",
          B"11111111111111111111010001111001");
Type rom_table_1 is Array (Natural range <>) of std_logic_vector(31 downto 0);
constant c1 : rom_table_1 := (
     B"00000000000000000000000000000000",
     B"00000000000000000001001100110100",
     B"00000000000000000010100010111110",
     B"00000000000000000011100110011110");
Type rom_table_2 is Array (Natural range <>) of std_logic_vector(31 downto 0);
constant c2 : rom_table_2 := (
B"00000000000000000011111110011100",
B"00000000000000000011100110011110",
B"00000000000000000010100010111110",
B"00000000000000000001001100110100");
Type rom_table_3 is Array (Natural range <>) of std_logic_vector(31 downto 0);
constant c3 : rom_table_3 := (
B"00000000000000000000000000000000",
B"11111111111111111111010001111001",
B"11111111111111111111001001101011",
B"11111111111111111111011111000100");


-- state register & states
type STATE_TYPE is (s0, s1, s2, s3);
signal STATE             : STATE_TYPE;
type CONTROL is (
alwayssampledonedwn,
alwaysshift,
alwayscompute,
alwaysdoneup
);
signal cmd : CONTROL;


begin

-- register updates
dpREG: process (CLK, RST)
begin
if (RST = '1') then
full0 <= (others => '0');
full1 <= (others => '0');
full2 <= (others => '0');
full3 <= (others => '0');
tap0 <= (others => '0');
tap1 <= (others => '0');
tap2 <= (others => '0');
tap3 <= (others => '0');
Yinp <= (others => '0');
Xinp <= (others => '0');
datap <= (others => '0');
streg <= '0';
dnreg <= '0';
elsif CLK' event and CLK = '1' then
full0 <= full0_wire;
full1 <= full1_wire;
full2 <= full2_wire;
full3 <= full3_wire;
tap0 <= tap0_wire;
tap1 <= tap1_wire;
tap2 <= tap2_wire;
tap3 <= tap3_wire;
Yinp <= Yinp_wire;
Xinp <= Xinp_wire;
datap <= datap_wire;
streg <= streg_wire;
dnreg <= dnreg_wire;
end if;
end process dpREG;


-- combinational logics
dpCMB: process (full0, full1, full2, full3, tap0, tap1, tap2, tap3, op_phase0, op_phase1
, op_phase2, op_phase3, Yinp, Xinp, datap, streg, dnreg, sig_0, sig_1, sig_2
, sig_3, sig_4, sig_5, sig_6, sig_7, sig_8, sig_9, sig_10, sig_11, sig_12
, sig_13, sig_14, sig_15, sig_16, sig_17, sig_18, sig_19, sig_20, sig_21, sig_22
, sig_23, sig_24, sig_25, sig_26, sig_27, sig_28, sig_29, sig_30, sig_31, sig_32
, sig_33, sig_34, sig_35, sig_36, sig_37, sig_38, sig_39, sig_40, sig_41, sig_42
, sig_43, sig_44, sig_45, sig_46, sig_47, sig_48, sig_49, sig_50, sig_51, sig_52
, sig_53, done_int, result_int, dataa, datab, start, clk_en,cmd,STATE)
begin
full0_wire <= full0;
full1_wire <= full1;
full2_wire <= full2;
full3_wire <= full3;
tap0_wire <= tap0;
tap1_wire <= tap1;
tap2_wire <= tap2;
tap3_wire <= tap3;
op_phase0 <= (others => '0');
op_phase1 <= (others => '0');
op_phase2 <= (others => '0');
op_phase3 <= (others => '0');
Yinp_wire <= Yinp;
Xinp_wire <= Xinp;
datap_wire <= datap;
streg_wire <= streg;
dnreg_wire <= dnreg;
sig_0 <= '0';
sig_1 <= '0';
sig_2 <= '0';
sig_3 <= '0';
sig_4 <= (others => '0');
sig_5 <= (others => '0');
sig_6 <= (others => '0');
sig_7 <= (others => '0');
sig_8 <= (others => '0');
sig_9 <= (others => '0');
sig_10 <= (others => '0');
sig_11 <= (others => '0');
sig_12 <= (others => '0');
sig_13 <= (others => '0');
sig_14 <= (others => '0');
sig_15 <= (others => '0');
sig_16 <= (others => '0');
sig_17 <= (others => '0');
sig_18 <= (others => '0');
sig_19 <= (others => '0');
sig_20 <= (others => '0');
sig_21 <= (others => '0');
sig_22 <= (others => '0');
sig_23 <= (others => '0');
sig_24 <= (others => '0');
sig_25 <= (others => '0');
sig_26 <= (others => '0');
sig_27 <= (others => '0');
sig_28 <= (others => '0');
sig_29 <= (others => '0');
sig_30 <= (others => '0');
sig_31 <= (others => '0');
sig_32 <= (others => '0');
sig_33 <= (others => '0');
sig_34 <= (others => '0');
sig_35 <= (others => '0');
sig_36 <= (others => '0');
sig_37 <= (others => '0');
sig_38 <= (others => '0');
sig_39 <= (others => '0');
sig_40 <= (others => '0');
sig_41 <= (others => '0');
sig_42 <= (others => '0');
sig_43 <= (others => '0');
sig_44 <= (others => '0');
sig_45 <= (others => '0');
sig_46 <= (others => '0');
sig_47 <= (others => '0');
sig_48 <= (others => '0');
sig_49 <= (others => '0');
sig_50 <= (others => '0');
sig_51 <= (others => '0');
sig_52 <= (others => '0');
sig_53 <= (others => '0');
done_int <= '0';
result_int <= (others => '0');
result <= (others => '0');
done <= '0';

case cmd is
when alwayssampledonedwn =>
done <= done_int;
if (signed(dataa) = 2) then
sig_0 <= '1';
else
sig_0 <= '0';
end if;
if (signed(dataa) = 3) then
sig_1 <= '1';
else
sig_1 <= '0';
end if;
if (signed(dataa) = 4) then
sig_2 <= '1';
else
sig_2 <= '0';
end if;
if (signed(dataa) = 5) then
sig_3 <= '1';
else
sig_3 <= '0';
end if;
if (sig_3 = '1') then
sig_4 <= op_phase3;
else
sig_4 <= std_logic_vector(to_unsigned(0, 32));
end if;
if (sig_0 = '1') then
sig_5 <= op_phase0;
elsif (sig_1 = '1') then
sig_5 <= op_phase1;
elsif (sig_2 = '1') then
sig_5 <= op_phase2;
else
sig_5 <= sig_4;
end if;
result <= result_int;
sig_6 <= std_logic_vector(shift_right(signed(full0), 14));
op_phase0 <= sig_6;
sig_7 <= std_logic_vector(shift_right(signed(full1), 14));
op_phase1 <= sig_7;
sig_8 <= std_logic_vector(shift_right(signed(full2), 14));
op_phase2 <= sig_8;
sig_9 <= std_logic_vector(shift_right(signed(full3), 14));
op_phase3 <= sig_9;
done_int <= dnreg;
result_int <= sig_5;
Xinp_wire <= dataa;
Yinp_wire <= datab;
streg_wire <= start;
dnreg_wire <= '0';
when alwaysshift =>
done <= done_int;
if (signed(dataa) = 2) then
sig_0 <= '1';
else
sig_0 <= '0';
end if;
if (signed(dataa) = 3) then
sig_1 <= '1';
else
sig_1 <= '0';
end if;
if (signed(dataa) = 4) then
sig_2 <= '1';
else
sig_2 <= '0';
end if;
if (signed(dataa) = 5) then
sig_3 <= '1';
else
sig_3 <= '0';
end if;
if (sig_3 = '1') then
sig_4 <= op_phase3;
else
sig_4 <= std_logic_vector(to_unsigned(0, 32));
end if;
if (sig_0 = '1') then
sig_5 <= op_phase0;
elsif (sig_1 = '1') then
sig_5 <= op_phase1;
elsif (sig_2 = '1') then
sig_5 <= op_phase2;
else
sig_5 <= sig_4;
end if;
result <= result_int;
sig_6 <= std_logic_vector(shift_right(signed(full0), 14));
op_phase0 <= sig_6;
sig_7 <= std_logic_vector(shift_right(signed(full1), 14));
op_phase1 <= sig_7;
sig_8 <= std_logic_vector(shift_right(signed(full2), 14));
op_phase2 <= sig_8;
sig_9 <= std_logic_vector(shift_right(signed(full3), 14));
op_phase3 <= sig_9;
done_int <= dnreg;
result_int <= sig_5;
Xinp_wire <= dataa;
Yinp_wire <= datab;
streg_wire <= start;
tap0_wire <= Yinp;
tap1_wire <= tap0;
tap2_wire <= tap1;
tap3_wire <= tap2;
when alwayscompute =>
done <= done_int;
if (signed(dataa) = 2) then
sig_0 <= '1';
else
sig_0 <= '0';
end if;
if (signed(dataa) = 3) then
sig_1 <= '1';
else
sig_1 <= '0';
end if;
if (signed(dataa) = 4) then
sig_2 <= '1';
else
sig_2 <= '0';
end if;
if (signed(dataa) = 5) then
sig_3 <= '1';
else
sig_3 <= '0';
end if;
if (sig_3 = '1') then
sig_4 <= op_phase3;
else
sig_4 <= std_logic_vector(to_unsigned(0, 32));
end if;
if (sig_0 = '1') then
sig_5 <= op_phase0;
elsif (sig_1 = '1') then
sig_5 <= op_phase1;
elsif (sig_2 = '1') then
sig_5 <= op_phase2;
else
sig_5 <= sig_4;
end if;
result <= result_int;
sig_6 <= std_logic_vector(shift_right(signed(full0), 14));
op_phase0 <= sig_6;
sig_7 <= std_logic_vector(shift_right(signed(full1), 14));
op_phase1 <= sig_7;
sig_8 <= std_logic_vector(shift_right(signed(full2), 14));
op_phase2 <= sig_8;
sig_9 <= std_logic_vector(shift_right(signed(full3), 14));
op_phase3 <= sig_9;
done_int <= dnreg;
result_int <= sig_5;
Xinp_wire <= dataa;
Yinp_wire <= datab;
streg_wire <= start;
sig_10 <= c3(to_integer(to_unsigned(0, 32)));
sig_11 <= std_logic_vector(signed(tap0) * signed(sig_10));
sig_12 <= c2(to_integer(to_unsigned(0, 32)));
sig_13 <= std_logic_vector(signed(tap1) * signed(sig_12));
sig_14 <= std_logic_vector(signed(sig_11) + signed(sig_13));
sig_15 <= c1(to_integer(to_unsigned(0, 32)));
sig_16 <= std_logic_vector(signed(tap2) * signed(sig_15));
sig_17 <= std_logic_vector(signed(sig_14) + signed(sig_16));
sig_18 <= c0(to_integer(to_unsigned(0, 32)));
sig_19 <= std_logic_vector(signed(tap3) * signed(sig_18));
sig_20 <= std_logic_vector(signed(sig_17) + signed(sig_19));
sig_21 <= c3(to_integer(to_unsigned(1, 32)));
sig_22 <= std_logic_vector(signed(tap0) * signed(sig_21));
sig_23 <= c2(to_integer(to_unsigned(1, 32)));
sig_24 <= std_logic_vector(signed(tap1) * signed(sig_23));
sig_25 <= std_logic_vector(signed(sig_22) + signed(sig_24));
sig_26 <= c1(to_integer(to_unsigned(1, 32)));
sig_27 <= std_logic_vector(signed(tap2) * signed(sig_26));
sig_28 <= std_logic_vector(signed(sig_25) + signed(sig_27));
sig_29 <= c0(to_integer(to_unsigned(1, 32)));
sig_30 <= std_logic_vector(signed(tap3) * signed(sig_29));
sig_31 <= std_logic_vector(signed(sig_28) + signed(sig_30));
sig_32 <= c3(to_integer(to_unsigned(2, 32)));
sig_33 <= std_logic_vector(signed(tap0) * signed(sig_32));
sig_34 <= c2(to_integer(to_unsigned(2, 32)));
sig_35 <= std_logic_vector(signed(tap1) * signed(sig_34));
sig_36 <= std_logic_vector(signed(sig_33) + signed(sig_35));
sig_37 <= c1(to_integer(to_unsigned(2, 32)));
sig_38 <= std_logic_vector(signed(tap2) * signed(sig_37));
sig_39 <= std_logic_vector(signed(sig_36) + signed(sig_38));
sig_40 <= c0(to_integer(to_unsigned(2, 32)));
sig_41 <= std_logic_vector(signed(tap3) * signed(sig_40));
sig_42 <= std_logic_vector(signed(sig_39) + signed(sig_41));
sig_43 <= c3(to_integer(to_unsigned(3, 32)));
sig_44 <= std_logic_vector(signed(tap0) * signed(sig_43));
sig_45 <= c2(to_integer(to_unsigned(3, 32)));
sig_46 <= std_logic_vector(signed(tap1) * signed(sig_45));
sig_47 <= std_logic_vector(signed(sig_44) + signed(sig_46));
sig_48 <= c1(to_integer(to_unsigned(3, 32)));
sig_49 <= std_logic_vector(signed(tap2) * signed(sig_48));
sig_50 <= std_logic_vector(signed(sig_47) + signed(sig_49));
sig_51 <= c0(to_integer(to_unsigned(3, 32)));
sig_52 <= std_logic_vector(signed(tap3) * signed(sig_51));
sig_53 <= std_logic_vector(signed(sig_50) + signed(sig_52));
full0_wire <= std_logic_vector(resize(signed(sig_20), 32));
full1_wire <= std_logic_vector(resize(signed(sig_31), 32));
full2_wire <= std_logic_vector(resize(signed(sig_42), 32));
full3_wire <= std_logic_vector(resize(signed(sig_53), 32));
when alwaysdoneup =>
done <= done_int;
if (signed(dataa) = 2) then
sig_0 <= '1';
else
sig_0 <= '0';
end if;
if (signed(dataa) = 3) then
sig_1 <= '1';
else
sig_1 <= '0';
end if;
if (signed(dataa) = 4) then
sig_2 <= '1';
else
sig_2 <= '0';
end if;
if (signed(dataa) = 5) then
sig_3 <= '1';
else
sig_3 <= '0';
end if;
if (sig_3 = '1') then
sig_4 <= op_phase3;
else
sig_4 <= std_logic_vector(to_unsigned(0, 32));
end if;
if (sig_0 = '1') then
sig_5 <= op_phase0;
elsif (sig_1 = '1') then
sig_5 <= op_phase1;
elsif (sig_2 = '1') then
sig_5 <= op_phase2;
else
sig_5 <= sig_4;
end if;
result <= result_int;
sig_6 <= std_logic_vector(shift_right(signed(full0), 14));
op_phase0 <= sig_6;
sig_7 <= std_logic_vector(shift_right(signed(full1), 14));
op_phase1 <= sig_7;
sig_8 <= std_logic_vector(shift_right(signed(full2), 14));
op_phase2 <= sig_8;
sig_9 <= std_logic_vector(shift_right(signed(full3), 14));
op_phase3 <= sig_9;
done_int <= dnreg;
result_int <= sig_5;
Xinp_wire <= dataa;
Yinp_wire <= datab;
streg_wire <= start;
dnreg_wire <= '1';
when others =>
end case;
end process dpCMB;


-- controller reg
fsmREG: process (CLK, RST)
begin
if (RST = '1') then
STATE <= s0;
elsif CLK' event and CLK = '1' then
STATE <= STATE;
case STATE is
when s0 =>
if (sig_55 = '1') then
          STATE <= s1;
else
          STATE <= s0;
end if;
when s1 =>
     STATE <= s2;
when s2 =>
     STATE <= s3;
when s3 =>
     STATE <= s0;
when others =>
end case;
end if;
end process fsmREG;


-- controller cmb
fsmCMB: process (full0, full1, full2, full3, tap0, tap1, tap2, tap3, op_phase0, op_phase1
, op_phase2, op_phase3, Yinp, Xinp, datap, streg, dnreg, sig_0, sig_1, sig_2
, sig_3, sig_4, sig_5, sig_6, sig_7, sig_8, sig_9, sig_10, sig_11, sig_12
, sig_13, sig_14, sig_15, sig_16, sig_17, sig_18, sig_19, sig_20, sig_21, sig_22
, sig_23, sig_24, sig_25, sig_26, sig_27, sig_28, sig_29, sig_30, sig_31, sig_32
, sig_33, sig_34, sig_35, sig_36, sig_37, sig_38, sig_39, sig_40, sig_41, sig_42
, sig_43, sig_44, sig_45, sig_46, sig_47, sig_48, sig_49, sig_50, sig_51, sig_52
, sig_53, done_int, result_int, sig_54, sig_55, dataa, datab, start, clk_en,cmd,STATE)
begin
sig_54 <= '0';
sig_55 <= '0';
if (signed(Xinp) = 1) then
sig_54 <= '1';
else
sig_54 <= '0';
end if;
sig_55 <= sig_54 and streg;
cmd <= alwayssampledonedwn;
case STATE is
when s0 =>
if (sig_55 = '1') then
     cmd <= alwayssampledonedwn;
else
     cmd <= alwayssampledonedwn;
end if;
when s1 =>
     cmd <= alwaysshift;
when s2 =>
     cmd <= alwayscompute;
when s3 =>
     cmd <= alwaysdoneup;
when others =>
end case;
end process fsmCMB;

end RTL;