entity xxx is
port(a,b,c : in std_logic;
        Q : out std_logic)
end;

architecture rtl of xxx is
begin
    process(A,B)
    variable qv : std_logic_vector(0 to 2);
    begin
        if A = '0' then qv := (others => '0');
            elsif rising_edge(B) then if C = '0' then gv := not gv(2) & qv(0 to 1); else gv := not gv(1) & gv(0 to 1);
            end if;
        end if;
        Q <= qv(0);
    end process;
end rtl;