cs241

module pattern_1(CLK, led_red, led_green);
	input CLK;
	output [7:0] led_red, led_green;
	reg [7:0] led_red, led_green;

	always @(led_red)
		case({led_red, led_green})
			16'b1001100110011001: {led_red, led_green} = 16'b1100001111000011;
			16'b1100001111000011: {led_red, led_green} = 16'b0110011001100110;
			16'b0110011001100110: {led_red, led_green} = 16'b0011110000111100;
			16'b0011110000111100: {led_red, led_green} = 16'b1001100110011001;
		endcase

endmodule