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Nov 28th, 2014
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3.  
  4.  
  5. entity temporizador is
  6. generic (fclk: integer := 1); -- frequencia do clock
  7. PORT (clk,clk2, rst, enable: in STD_LOGIC;--clk 2 tem que ser MUITO ALTO
  8. B2 : in std_LOGIC;
  9. buzina: out STD_LOGIC;
  10. D : out STD_LOGIC_VECTOR (0 to 6); -- saida decodificada
  11. saida : out std_logic_vector (1 downto 0)
  12.  
  13. );
  14. end temporizador;
  15.  
  16. ARCHITECTURE temporizador_arc OF temporizador IS
  17. SIGNAL dig1,dig2 : STD_LOGIC_VECTOR (0 to 6);
  18.  
  19. BEGIN
  20.  
  21.  
  22. PROCESS(clk, rst, enable, B2)
  23.  
  24. VARIABLE count0: INTEGER RANGE 0 TO fclk; --para 1Hz
  25. VARIABLE count1: INTEGER RANGE 0 TO 10; -- para o primeiro digito
  26. VARIABLE count2: INTEGER RANGE 0 TO 7; -- para o segundo digito
  27. BEGIN
  28. -- contadores
  29. if (rst = '1') then
  30. count0 := 0;
  31. count1 := 0;
  32. count2 := 0;
  33.  
  34. elsif(clk'event and clk='1') then
  35. buzina<='0';
  36. if (enable='1') then
  37. count0 := count0 + 1;
  38. if (count0 = fclk) then
  39. count0 :=0;
  40. count1 := count1 +1;
  41. if (count1=10) then
  42. count1 := 0;
  43. count2 := count2 +1;
  44. end if;
  45. if(count2=2) then
  46. buzina <='1';
  47. elsif(count2=4) then
  48. buzina <='1';
  49. count2:=0;
  50. elsif(count2=6) then
  51. buzina <='1';
  52. count2:=0;
  53. end if;
  54. if(B2='1') then
  55. buzina<='1';
  56. end if;
  57. end if;
  58. end if;
  59. end if;
  60.  
  61. -- display
  62.  
  63.  
  64.  
  65. CASE count1 IS
  66.  
  67. WHEN 0 => dig1 <= "1111110"; --126
  68. WHEN 1 => dig1 <= "0110000"; --48
  69. WHEN 2 => dig1 <= "1101101"; --109
  70. WHEN 3 => dig1 <= "1111001"; --121
  71. WHEN 4 => dig1 <= "0110011"; --51
  72. WHEN 5 => dig1 <= "1011011"; --91
  73. WHEN 6 => dig1 <= "1011111"; --95
  74. WHEN 7 => dig1 <= "1110000"; --112
  75. WHEN 8 => dig1 <= "1111111"; --127
  76. WHEN 9 => dig1 <= "1111011"; --123
  77. WHEN OTHERS => NULL;
  78. END CASE;
  79.  
  80.  
  81. CASE count2 IS
  82. WHEN 0 => dig2 <= "1111110"; --126
  83. WHEN 1 => dig2 <= "0110000"; --48
  84. WHEN 2 => dig2 <= "1101101"; --109
  85. WHEN 3 => dig2 <= "1111001"; --121
  86. WHEN 4 => dig2 <= "0110011"; --51
  87. WHEN 5 => dig2 <= "1011011"; --91
  88. WHEN 6 => dig2 <= "1011111"; --95
  89. WHEN OTHERS => NULL;
  90. END CASE;
  91.  
  92. END PROCESS;
  93.  
  94. process (clk2)
  95. begin
  96.  
  97. if (clk2='0') then
  98. saida <= "01";
  99. D<= dig1;
  100. else
  101. saida <= "10";
  102. D<= dig2;
  103. end if;
  104. end process;
  105. END temporizador_arc;
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