16 bit carry look ahead

timescale 1ns / 1ps

module Partial_Add(output P,G,S,
						input A,B,Ci	);
//Gate modeling of Partial adder
					xor Prop(P,A,B);
					xor Sum(S,A,B,Ci);
					and Gen(G,A,B);

endmodule

module Carry_look(output Pg,Gg,
					output [3:0] Cout ,
					input [3:0] P,G,
					input Ci);

			wire P0Ci;
			and(P0Ci,P[0],Ci);
			or (Cout[0],G[0],P0Ci);

			wire P1G0;
			wire P1P0;
			and (P1G0,P[1],G[0]);
			and (P1P0Ci,P[1],P[0],Ci);
			or (Cout[1],G[1],P1G0,P1P0Ci);

			wire P2G1;
			wire P2P2G0;
			wire P2P1P0;
			and (P2G1,P[2],G[1]);
			and (P2P1G0,P[2],P[1],G[0]);
			and (P2P1P0Ci,P[2],P[1],P[0],Ci);
			or (Cout[2],G[2],P2G1,P2P1G0,P2P1P0Ci);

			wire P3G2;
			wire P3P2G1;
			wire P3P2P1G0;
			wire P3P2P1;
			and (P3G2,P[3],G[2]);
			and (P3P2G1,P[3],P[2],G[1]);
			and (P3P2P1G0,P[3],P[2],P[1],G[0]);
			and (P3P2P1Ci,P[3],P[2],P[1],Ci);
			or (Cout[3],G[3],P3G2,P3P2G1,P3P2P1G0,P3P2P1Ci);

			or (Gg,G[3],P3G2,P3P2G1,P3P2P1G0);
			and(Pg,P);

endmodule

module Carry_look_4bit(output Co,
							output [3:0] S,
							output Pg,Gg,
							input [3:0] A,B,
							input Ci);
							wire [3:0] Car;
							wire [3:0] P,G;

		//This will put all the Partial adders and the CLA together
		Partial_Add add[3:0](.P(P),.G(G),.S(S),.A(A),.B(B),.Ci(Car));		//P takes P as input etc
		Carry_look CLA1(.Pg(Pg),.Gg(Gg),.Cout(Car),.P(P),.G(G),.Ci(Ci));   	//Pu takes Pu as input etc


assign Co=Car[3];		//Co will be Carry 3
endmodule

module LookAhead_16b(output Co,
							output [15:0] S,
							input [15:0] A,B,
							input Ci);
					wire [3:0] Car;
					wire [3:0] P;
					wire [3:0] G;
					wire Pg;
					wire Gg;
					wire C1;
					wire C2;
					wire C3;
					wire C4;
					//These are the 4, 4 bit Carry looks with their respected inputs and lines defined
		Carry_look_4bit A1 (.Co(C1),.S(S[3:0]),.Pg(P[0]),.Gg(G[0]),.A(A[3:0]),.B(B[3:0]),.Ci(Ci));
		Carry_look_4bit A2 (.Co(C2),.S(S[7:4]),.Pg(P[1]),.Gg(G[1]),.A(A[7:4]),.B(B[7:4]),.Ci(Car[0]));
		Carry_look_4bit A3 (.Co(C3),.S(S[11:8]),.Pg(P[2]),.Gg(G[2]),.A(A[11:8]),.B(B[11:8]),.Ci(Car[1]));
		Carry_look_4bit A4 (.Co(C4),.S(S[15:12]),.Pg(P[3]),.Gg(G[3]),.A(A[15:12]),.B(B[15:12]),.Ci(Car[2]));

		Carry_look CLA2(.Pg(Pg),.Gg(Gg),.Cout(Car),.P(P),.G(G),.Ci(Ci));
		//This makes the carry out, the last carry of the last CLA


assign Co = Car[3];

endmodule