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altera

By: a guest | Mar 22nd, 2010 | Syntax: None | Size: 0.29 KB | Hits: 54 | Expires: Never
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  1. LIBRARY ieee ;
  2. USE ieee.std_logic_1164.all ;
  3. USE ieee.std_logic_signed.all ;
  4.  
  5. ENTITY adder16 IS
  6.         PORT (  X, Y    : IN    STD_LOGIC_VECTOR(15 DOWNTO 0) ;
  7.                 S       : OUT   STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
  8. END adder16 ;
  9.  
  10. ARCHITECTURE Behavior OF adder16 IS    
  11. BEGIN
  12.         S <= X + Y ;
  13. END Behavior ;
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