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  1. /* FSE_parse_opcode: parsing opcodes from generated code
  2. * In: $r10: pointer to generated code
  3. *Out: none
  4. */
  5.  
  6. FSE_parse_opcode:
  7. push $r1
  8. push $r2
  9. push $r3
  10. push $r4
  11. push $r5
  12. push $r6
  13. push $r7
  14. push $r8
  15. push $r9
  16.  
  17. FSE_parse_opcode_loop:
  18. /* store the opcodes */
  19. mov $r1 0x00
  20. mov $r2 0x01
  21. mov $r3 0x02
  22. mov $r4 0x10
  23. mov $r5 0x11
  24. mov $r6 0x12
  25. mov $r7 0x13
  26. mov $r8 0x20
  27. mov $r9 0xff
  28.  
  29. mov b32 $r15 $r10
  30.  
  31. /* load the first position of generated code */
  32. ld b8 $r11 D[$r15 + 0]
  33.  
  34. cmpu b8 $r11 $r1
  35. bra e #FSE_delay_ns_fr
  36.  
  37. cmpu b8 $r11 $r2
  38. bra e #FSE_delay_ns
  39.  
  40. cmpu b8 $r11 $r3
  41. bra e #FSE_delay_us
  42.  
  43. cmpu b8 $r11 $r4
  44. bra e #FSE_write
  45.  
  46. cmpu b8 $r11 $r5
  47. bra e #FSE_write_b8
  48.  
  49. cmpu b8 $r11 $r6
  50. bra e #FSE_mask
  51.  
  52. cmpu b8 $r11 $r7
  53. bra e #FSE_wait
  54.  
  55. cmpu b8 $r11 $r8
  56. bra e #FSE_send_msg
  57.  
  58. cmpu b8 $r11 $r9
  59. bra e #FSE_exit
  60.  
  61. /* unknown opcode*/
  62. mov $r10 0
  63. bra #FSE_exit
  64.  
  65. /* Full range delay */
  66. FSE_delay_ns_fr:
  67. mov b32 $r1 $r15
  68.  
  69. /* ld b32 $r10 D[$r1 + 1] */
  70. add b32 $r10 $r1 1
  71. call #ld_32
  72.  
  73. /* r2 = r10 = HIGH */
  74. mov b32 $r2 $r10
  75.  
  76. /* ld b32 $r11 D[$r1 + 5] */
  77. add b32 $r10 $r1 5
  78. call #ld_32
  79.  
  80. /* r11 = r10 = LOW */
  81. mov b32 $r11 $r10
  82.  
  83. /* r10 = r2 = HIGH */
  84. mov b32 $r10 $r2
  85.  
  86. /* r10 = HIGH r11 = LOW */
  87. call #sleep_ns
  88.  
  89. /* Position + 9 */
  90. add b32 $r10 $r1 9
  91. bra #FSE_parse_opcode_loop
  92.  
  93. FSE_delay_ns:
  94. mov b32 $r1 $r15
  95.  
  96. /* ld b32 $r11 D[$r1 + 1] */
  97. /* r11 = LOW */
  98. add b32 $r10 $r1 1
  99. call #ld_16
  100. mov b32 $r11 $r10
  101.  
  102. /* r10 = HIGH = 0 */
  103. mov $r10 0x0
  104. call #sleep_ns
  105.  
  106. add b32 $r10 $r1 3
  107. bra #FSE_parse_opcode_loop
  108.  
  109. FSE_delay_us:
  110. mov b32 $r1 $r15
  111.  
  112. /* ld b32 $r11 D[$r1 + 1] */
  113. /* r11 = LOW */
  114. add b32 $r10 $r1 1
  115. call #ld_16
  116. mov b32 $r11 $r10
  117.  
  118. mulu $r11 1000
  119.  
  120. /* r10 = HIGH = 0 */
  121. mov $r10 0x0
  122. call #sleep_ns
  123.  
  124. add b32 $r10 $r1 3
  125. bra #FSE_parse_opcode_loop
  126.  
  127. FSE_write:
  128. mov b32 $r1 $r15
  129.  
  130. /* r2 = REG */
  131. /* ld b32 $r2 D[$r1 + 1] */
  132. add b32 $r10 $r1 1
  133. call #ld_32
  134. mov b32 $r2 $r10
  135.  
  136. /* r11 = VAL */
  137. /* ld b32 $r11 D[$r1 + 5] */
  138. add b32 $r10 $r1 5
  139. call #ld_32
  140. mov b32 $r11 $r10
  141.  
  142. /* r10 = r2 = reg */
  143. mov b32 $r10 $r2
  144. call #mmwr
  145.  
  146. add b32 $r10 $r1 9
  147. bra #FSE_parse_opcode_loop
  148.  
  149. FSE_write_b8:
  150. mov b32 $r1 $r15
  151.  
  152. /* r2 = REG */
  153. /* ld b32 $r2 D[$r1 + 1] */
  154. add b32 $r10 $r1 1
  155. call #ld_32
  156. mov b32 $r2 $r10
  157.  
  158. /* r11 = VAL */
  159. /* ld b8 $r11 D[$r1 + 5] */
  160. add b32 $r10 $r1 5
  161. call #ld_08
  162. mov b32 $r11 $r10
  163.  
  164. /* r10 = r2 = reg */
  165. mov b32 $r10 $r2
  166.  
  167. call #mmwr
  168.  
  169. add b32 $r10 $r1 6
  170. bra #FSE_parse_opcode_loop
  171.  
  172. FSE_mask:
  173. mov b32 $r1 $r15
  174.  
  175. /* r2 = REG */
  176. /* ld b32 $r2 D[$r1 + 1] */
  177. add b32 $r10 $r1 1
  178. call #ld_32
  179. mov b32 $r2 $r10
  180.  
  181. /* r3 = MASK */
  182. /* ld b32 $r3 D[$r1 + 5] */
  183. add b32 $r10 $r1 5
  184. call #ld_32
  185. mov b32 $r3 $r10
  186.  
  187. /* r4 = DATA */
  188. /* ld b32 $r4 D[$r1 + 9] */
  189. add b32 $r10 $r1 9
  190. call #ld_32
  191. mov b32 $r4 $r10
  192.  
  193. mov b32 $r10 $r2
  194. call #mmrd
  195.  
  196. and $r11 $r10 $r3
  197. or $r11 $r11 $r4
  198.  
  199. mov b32 $r10 $r2
  200.  
  201. call #mmwr
  202.  
  203. add b32 $r10 $r1 13
  204. bra #FSE_parse_opcode_loop
  205.  
  206. FSE_wait:
  207. mov b32 $r1 $r15
  208.  
  209. /* r2 = REG */
  210. /* ld b32 $r2 D[$r1 + 1] */
  211. add b32 $r10 $r1 1
  212. call #ld_32
  213. mov b32 $r2 $r10
  214.  
  215. /* r3 = MASK */
  216. /* ld b32 $r3 D[$r1 + 5] */
  217. add b32 $r10 $r1 5
  218. call #ld_32
  219. mov b32 $r3 $r10
  220.  
  221. /* r4 = DATA */
  222. /* ld b32 $r4 D[$r1 + 9] */
  223. add b32 $r10 $r1 9
  224. call #ld_32
  225. mov b32 $r4 $r10
  226.  
  227. FSE_wait_loop:
  228. mov b32 $r10 $r2
  229. call #mmrd
  230.  
  231. and $r11 $r10 $r3
  232. cmpu b32 $r11 $r4
  233. bra ne #FSE_wait_loop
  234.  
  235. add b32 $r10 $r1 13
  236. bra #FSE_parse_opcode_loop
  237.  
  238. FSE_send_msg:
  239. mov b32 $r1 $r15
  240.  
  241. /* r12 = payload_size */
  242. /*ld b16 $r12 D[$r1 + 1] */
  243. add b32 $r10 $r1 1
  244. call #ld_16
  245. mov b32 $r12 $r10
  246.  
  247. /* r13 = start of payload */
  248. add b32 $r13 $r1 3
  249.  
  250. /*store incremented pointer*/
  251. add b32 $r1 $r1 3
  252. add b32 $r1 $r1 $r12
  253.  
  254. /* Add value $r11:msg_id */
  255. mov $r11 0x02
  256.  
  257. /* pid = r10 = 0x02 */
  258. mov $r10 0x02
  259. call #rdispatch_send_msg
  260.  
  261. mov b32 $r10 $r1
  262. bra #FSE_parse_opcode_loop
  263.  
  264. FSE_exit:
  265.  
  266. pop $r9
  267. pop $r8
  268. pop $r7
  269. pop $r6
  270. pop $r5
  271. pop $r4
  272. pop $r3
  273. pop $r2
  274. pop $r1
  275.  
  276. ret
');