architecture Behavioral of System is
  component Master is
    port (
      cs_vec : out std_logic_vector(k downto 0);
      done : out std_logic;
      clk : in std_logic;
      ...);
  end component;
  component Slave0 is
    port (
      cs : in std_logic;
      done : out std_logic;
      clk : in std_logic;
      ...);
  end component;

  ... # SlaveX component definitions

  cs_vec : std_logic_vector(k downto 0);
  done : std_logic;
begin
  master : Master
    port map (
        cs_vec => cs_vec,
        done => done,
        clk => clk,
        ...);
  slave0 : Slave0
    port map (
        cs => cs_vec(0),
        done => done,
        clk => clk,
        ...);

  ... # SlaveX instance definitions

  process(clk) begin
    if clk'event and clk = '1' then
      if cs_vec = std_logic_vector(0, cs_vec'length) then
        done <= '0';
      else
        done <= 'Z';
      end if;
    end if;
  end process;
end Behavioral;