.include "tn13Adef.inc"
.def txreg = r16
.def bitcnt = r17
.def txrdy = r18
.def tmp = r19
.def c = r20
//Pin assignments
.equ TXPIN = PB0
.equ M = 0x05
.cseg
; Interrupt Vectors
.org 0x00
rjmp RESET_Vect ; Reset Handler
rjmp EXT_INT0_Vect ; IRQ0 Handler
rjmp PCINT0_Vect ; PCINT0 Handler
rjmp TIM0_OVF_Vect ; Timer0 Overflow Handler
rjmp EE_RDY_Vect ; EEPROM Ready Handler
rjmp ANA_COMP_Vect ; Analog Comparator Handler
rjmp TIM0_COMPA_Vect ; Timer0 CompareA Handler
rjmp TIM0_COMPB_Vect ; Timer0 CompareB Handler
rjmp WDT_Vect ; Watchdog Interrupt Handler
rjmp ADC_Vect ; ADC Conversion Handler
EXT_INT0_Vect:
PCINT0_Vect:
TIM0_OVF_Vect:
EE_RDY_Vect:
ANA_COMP_Vect:
TIM0_COMPB_Vect:
WDT_Vect:
ADC_Vect:
RESET_Vect:
ldi tmp, low(RAMEND); Main program start
out SPL,tmp ; Set Stack Pointer to top of RAM
sei ; Enable interrupts
Main:
; Init Software TX
ldi txreg, 0
ldi bitcnt, 0
ldi tmp, (1<<PB0) ; configure PB0 for output
out DDRB, tmp
sbi PORTB, (1<<PB1)
; Setup Timer for 4800 bps bit shift operation
; CS00|CS01 -> 4.8MHz /8
; WGM01 -> CTC mode
; OCR0A -> /125 -> 4800Hz (0% error)
ldi tmp, (1<<WGM01)
out TCCR0A, tmp
ldi tmp, (1<<CS01)
out TCCR0B, tmp
ldi tmp,112;,125
out OCR0A, tmp
ldi tmp, (1<<OCIE0A) ; enable interrupts
out TIMSK0, tmp
cbi PORTB, (1<<PB1)
ldi c, 0x6D ; load character to transmit, 'm'
loop:
mov txreg, c ; send character
ldi bitcnt, 10 ; send start+8+stop bits (starts the shift-out of txreg)
wait:
cpi bitcnt, 0 ; when bitcnt==0 transmit is done, ready for next byte
brne wait
rcall delay ; after transmit, wait a fixed time delay
rjmp loop ; transmit the next character
delay: ; fixed time delay loop
push r18
push r19
push r20
; Generated by delay loop calculator
; at http://www.bretmulvey.com/avrdelay.html
;
; Delay 959 977 cycles
; 199ms 995us 208 1/3 ns
; at 4.8 MHz
ldi r18, 5
ldi r19, 223
ldi r20, 181
L1: dec r20
brne L1
dec r19
brne L1
dec r18
brne L1
pop r20
pop r19
pop r18
ret
TIM0_COMPA_Vect:
cpi bitcnt, 0 ; send stop until bitcnt reset to 10
breq SendStop
cpi bitcnt, 10 ; if first bit, send a start first
breq Send0 ; send start bit (low)
cpi bitcnt, 1 ; guarantee last bit is a stop bit
breq SendStop
lsr txreg ; shift off the next bit, LSB first
brcs Send1 ; if it is 1 (C=1) then send 1
Send0:
cbi PORTB, TXPIN ; 0=low
rjmp BitDone
Send1:
sbi PORTB, TXPIN ; 1=high
rjmp BitDone
SendStop:
sbi PORTB, TXPIN ; stop bit (high)
reti
BitDone:
dec bitcnt
reti