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  1. .include "tn13Adef.inc"
  2.  
  3. .def txreg = r16
  4. .def bitcnt = r17
  5. .def txrdy = r18
  6. .def tmp = r19
  7. .def c = r20
  8.  
  9. //Pin assignments
  10. .equ TXPIN = PB0
  11. .equ M = 0x05
  12.  
  13. .cseg
  14.  
  15. ; Interrupt Vectors
  16. .org 0x00
  17. rjmp RESET_Vect ; Reset Handler
  18. rjmp EXT_INT0_Vect ; IRQ0 Handler
  19. rjmp PCINT0_Vect ; PCINT0 Handler
  20. rjmp TIM0_OVF_Vect ; Timer0 Overflow Handler
  21. rjmp EE_RDY_Vect ; EEPROM Ready Handler
  22. rjmp ANA_COMP_Vect ; Analog Comparator Handler
  23. rjmp TIM0_COMPA_Vect ; Timer0 CompareA Handler
  24. rjmp TIM0_COMPB_Vect ; Timer0 CompareB Handler
  25. rjmp WDT_Vect ; Watchdog Interrupt Handler
  26. rjmp ADC_Vect ; ADC Conversion Handler
  27.  
  28. EXT_INT0_Vect:
  29. PCINT0_Vect:
  30. TIM0_OVF_Vect:
  31. EE_RDY_Vect:
  32. ANA_COMP_Vect:
  33. TIM0_COMPB_Vect:
  34. WDT_Vect:
  35. ADC_Vect:
  36.  
  37. RESET_Vect:
  38. ldi tmp, low(RAMEND); Main program start
  39. out SPL,tmp ; Set Stack Pointer to top of RAM
  40. sei ; Enable interrupts
  41.  
  42. Main:
  43. ; Init Software TX
  44. ldi txreg, 0
  45. ldi bitcnt, 0
  46. ldi tmp, (1<<PB0) ; configure PB0 for output
  47. out DDRB, tmp
  48. sbi PORTB, (1<<PB1)
  49. ; Setup Timer for 4800 bps bit shift operation
  50. ; CS00|CS01 -> 4.8MHz /8
  51. ; WGM01 -> CTC mode
  52. ; OCR0A -> /125 -> 4800Hz (0% error)
  53. ldi tmp, (1<<WGM01)
  54. out TCCR0A, tmp
  55. ldi tmp, (1<<CS01)
  56. out TCCR0B, tmp
  57. ldi tmp,112;,125
  58. out OCR0A, tmp
  59. ldi tmp, (1<<OCIE0A) ; enable interrupts
  60. out TIMSK0, tmp
  61. cbi PORTB, (1<<PB1)
  62.  
  63. ldi c, 0x6D ; load character to transmit, 'm'
  64. loop:
  65. mov txreg, c ; send character
  66. ldi bitcnt, 10 ; send start+8+stop bits (starts the shift-out of txreg)
  67. wait:
  68. cpi bitcnt, 0 ; when bitcnt==0 transmit is done, ready for next byte
  69. brne wait
  70. rcall delay ; after transmit, wait a fixed time delay
  71. rjmp loop ; transmit the next character
  72.  
  73. delay: ; fixed time delay loop
  74. push r18
  75. push r19
  76. push r20
  77.  
  78. ; Generated by delay loop calculator
  79. ; at http://www.bretmulvey.com/avrdelay.html
  80. ;
  81. ; Delay 959 977 cycles
  82. ; 199ms 995us 208 1/3 ns
  83. ; at 4.8 MHz
  84.  
  85. ldi r18, 5
  86. ldi r19, 223
  87. ldi r20, 181
  88. L1: dec r20
  89. brne L1
  90. dec r19
  91. brne L1
  92. dec r18
  93. brne L1
  94.  
  95. pop r20
  96. pop r19
  97. pop r18
  98. ret
  99.  
  100. TIM0_COMPA_Vect:
  101. cpi bitcnt, 0 ; send stop until bitcnt reset to 10
  102. breq SendStop
  103. cpi bitcnt, 10 ; if first bit, send a start first
  104. breq Send0 ; send start bit (low)
  105. cpi bitcnt, 1 ; guarantee last bit is a stop bit
  106. breq SendStop
  107. lsr txreg ; shift off the next bit, LSB first
  108. brcs Send1 ; if it is 1 (C=1) then send 1
  109.  
  110. Send0:
  111. cbi PORTB, TXPIN ; 0=low
  112. rjmp BitDone
  113. Send1:
  114. sbi PORTB, TXPIN ; 1=high
  115. rjmp BitDone
  116. SendStop:
  117. sbi PORTB, TXPIN ; stop bit (high)
  118. reti
  119. BitDone:
  120. dec bitcnt
  121. reti