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By: a guest on Mar 7th, 2012  |  syntax: VeriLog  |  size: 0.52 KB  |  hits: 66  |  expires: Never
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  1. module TopLevelTest(
  2.         clk_20mhz,
  3.         uart_rx, uart_tx,
  4.         i2c_sda, i2c_scl,
  5.         spi_cs_n, spi_mosi, spi_miso, spi_sck,
  6.         leds,
  7.         gpio
  8.     );
  9.          
  10.         ////////////////////////////////////////////////////////////////////////////////////////////////
  11.         // IO declarations
  12.  
  13.         input wire clk_20mhz;
  14.  
  15.         input wire uart_rx;
  16.         output wire uart_tx;
  17.        
  18.         output wire i2c_scl;
  19.         inout wire i2c_sda;
  20.        
  21.         output wire spi_cs_n;
  22.         output wire spi_mosi;
  23.         input wire spi_miso;
  24.         output wire spi_sck;
  25.        
  26.         output reg[7:0] leds = 0;
  27.  
  28.         inout wire[30:0] gpio;