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Mar 7th, 2012 | syntax:
VeriLog | size: 0.52 KB | hits: 66 | expires: Never
module TopLevelTest(
clk_20mhz,
uart_rx, uart_tx,
i2c_sda, i2c_scl,
spi_cs_n, spi_mosi, spi_miso, spi_sck,
leds,
gpio
);
////////////////////////////////////////////////////////////////////////////////////////////////
// IO declarations
input wire clk_20mhz;
input wire uart_rx;
output wire uart_tx;
output wire i2c_scl;
inout wire i2c_sda;
output wire spi_cs_n;
output wire spi_mosi;
input wire spi_miso;
output wire spi_sck;
output reg[7:0] leds = 0;
inout wire[30:0] gpio;