library IEEE;
use IEEE.std_logic_1164.ALL;

--entity--
entity clock_ex is
-- nothing inside because is only an example of clock process VS clock event
end clock_ex;

-- Architecture --

architecture CLKEX of clock_ex is

signal clk_p: std_logic :='0'; -- clock for process 2ns semiperiod
signal clk_e: std_logic :='0'; -- clock for event   1 ns

begin

clk_e <= not clk_e after 1 ns; -- change in the clock trough event
process
begin
clk_p <= not clk_p; -- change in the clock trough process
wait for 2 ns;
end process;

end;

process
variable stop_s: integer :=100; -- to stop the process
variable count_s: integer :=0; -- counter integer
begin
if(count_s < stop_s) then
clk_p <= not clk_p; -- change in the clock trough process
count_s:= count_s+1; -- change in the clock trough event
wait for 2 ns;
end if;
end process;